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NEC design tool analyzes power integrity within seconds

Posted: 22 Apr 2005 ?? ?Print Version ?Bookmark and Share

Keywords:power line design tool? notebook? pc?

Coping with a growing need for full-chip power integrity analysis of low supply voltage, high frequency and smaller geometry devices, NEC Corp. of Japan has developed a power line design tool that performs power integrity analysis in a fraction of the time of comparable tools.

"We wanted to develop a power line design tool that engineers can practically use," said Toshihide Kuriyama, a scientist at NEC Research Laboratories.

Power integrity analysis normally takes hours or even days and power-related changes are time-consuming. The lengthy time makes it difficult for engineers to experiment with placement of decoupling capacitors. With this tool, able to run on a notebook PC, engineers can quickly perform what-if analysis on the locations and size of decoupling capacitors required at early stages of design flow.

Increasing requirements for low voltage supply power have made power line noise of LSI chips a significant problem that can cause chip failure. In conventional design, power integrity optimization has been done when all physical design information is available.

"It costs much and takes time if the optimization is done at prototyping stage. The optimization should be done as early as possible on the design flow and the tool enables it," said Kuriyama.

For the time being, NEC intends to use the tool internally for its LSI design differentiation, but expects the precise data from the tool will contribute to standardization of power methodology. The company is presenting the design system at the EMC Noise Countermeasures Technological Exhibition this week in Makuhari, near Tokyo.

- Yoshiko Hara

EE Times





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