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Cadence PCI Express solution passes PCI-SIG testing

Posted: 27 Apr 2005 ?? ?Print Version ?Bookmark and Share

Keywords:pex endpoint controller ip? pci express phy ip? rambus? pci-sig?

Cadence Design Systems Inc. announced that its PEX endpoint controller IP, integrated with Rambus' PCI Express PHY IP, has passed PCI-SIG compliance testing and been added to the PCI-SIG integrators list.

Cadence has taken a vertical approach to meeting the needs of PCI Express customers, combining technologies from industry leaders to enable customers to reduce risk and increase productivity. In addition to design and verification IP, the vertical approach combines emulation, board design and protocol analysis tools targeted at the PCI Express architecture. In preparing for the compliance workshop, where devices need to pass compliance and interoperability testing, verification IP from Denali and PCI Express analyzers from Catalyst helped Cadence develop a higher-quality product.

Passing compliance testing is a significant milestone for the serial link portfolio agreement announced in July 2004 between Cadence and Rambus. In March, Cadence and Rambus announced that Open-Silicon, a fabless ASIC company, licensed multiple Rambus RaSer serial link offerings through the Cadence-Rambus reseller program.

The PCI Express technology has become established as a high-speed serial interconnect. However, its complex digital protocol layers and multi-GigaHertz analog interfaces make design and verification more complex.





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