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It's time to move DFT to a higher level

Posted: 02 May 2005 ?? ?Print Version ?Bookmark and Share

Keywords:asic? dft? eda? ip? rtl?

Aktouf: The way to enhance DFT processes and increase the testability of SoC is DFT at the RTL.

ASIC design for test (DFT) is about to become the next bottleneck in EDA. Current DFT solutions on the market apply only to post-synthesis gate-level netlists, which results in high development costs and unpredictable development times. Not only that, current solutions do not address intellectual property (IP) exchange needs.

Today, most design functions are written and specified at the register-transfer level (RTL). Very soon, they will be written and specified at the electronic system level (esl). If DFT continues to be done post-synthesis, it will be farther and farther from the point at which design decisions are made. Quality will also be compromised in new deep-submicron technologies because of the appearance of new defect types.

After designs are written and specified, the remaining design steps before tapeout are compilation, optimization and verification. Even now, the cost to manufacture chips approaches the cost of testing them, as reported by the International Technology Roadmap for Semiconductors. To cope with cost and quality challenges, big semiconductor companies require an increasing amount of DFT, a trend that is only expected to continue.

Using DFT methods such as scan and bist is not in question. The shortcoming is the lack of massive, cost-effective and efficient implementation of all necessary DFT methods that will guarantee testability and testing requirementsearly in the design cycle.

New DFT solutions will have to cope with the increasing cost of designs. And since DFT is estimated to represent 10 to 25 percent of total design cost and is growing, new DFT solutions will also have to become a diminishing percentage of overall design. This challenge will be difficult to meet as chips become larger and more complex, and are required to integrate external IP.

One of the main difficulties is the widening gap between traditional DFT solutions and the evolution of design flows and methodologies. Being tied to logic synthesis and gate-level representation, today's DFT solutions are still one step lower in design methodology than most other design steps, which are reusable and technology-independent. This increases design costs and directly impacts time-to-market.

Here's where an old engineering "rule-of-thumb" comes into play. Detecting, isolating and resolving a problem at any stage of the design, implementation or deployment process costs 10 times more than addressing the same problem at the previous stage in the process. In the case of digital ICs, there are three major levels of abstraction in the design flow where DFT is considered: RTL, gate level and layout. DFT insertion, which is now being employed at the gate level, implicitly places a tenfold burden on the designer dealing with DFT aspects of the circuit.

Design abstraction has always guided important changes in design flow. The progress to EDA methodologies cannot simply end with RTL. DFT is becoming one of the most critical design steps because many other steps depend on it. By leaving DFT at the gate level, we are turning this critical step into a bottleneck. As EDA moves unavoidably to ESL, interoperability between design steps will worsen.

The way to enhance DFT processes and increase the testability of SoC is DFT at the RTL. By streamlining the overall design flow, RTL DFT will be an effective way to strengthen quality and improve cost-effectiveness. Of course, new solutions, starting with mature DFT methods such as scan and BIST, will have to demonstrate quality and improve existing design flows without disruption.

Today, the "D" in DFT does not really stand for design. All too often, at the gate level, it stands for do-it-late. The semiconductor industry needs to move DFT upfront in the design cycle to enjoy the benefits of really designing for test.

- Chouki Aktouf
President and CTO
DeFacTo Technologies

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