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Initiative brings low power to mainstream design

Posted: 02 May 2005 ?? ?Print Version ?Bookmark and Share

Keywords:cadence? arm? tsmc? low power? effective current source model?

Collaboration is the best way to make low-power design accessible to mainstream IC designers, according to four suppliers claiming a design flow that achieves a 40 percent power savings for 90nm chip designs.

Cadence Design Systems Inc., ARM Ltd, Applied Materials Inc. and Taiwan Semiconductor Manufacturing Co. Ltd used Cadence design tools and ARM libraries to achieve the savings on an ARM1136JF-S test chip. The four had earlier founded the Silicon Design Chain Initiative to develop low-power design flows.

To save power, Cadence and ARM developed a new way to insert level shifters into multiple-supply-voltage (MSV) designs. They also extended Cadence's effective current-source model (ECSM) format across multiple voltage ranges. The moves reportedly resulted in a 37.9 percent improvement in dynamic power and a 46.7 percent improvement in leakage powera total savings of 40.3 percent over the same design done previously with the same tools.

The point, Silicon Design Chain Initiative members say, is that low-power 90nm designs need no longer be restricted to power users. "In 2005, low-power design needs to be brought to the mainstream," said George Kuo, Cadence's technical director of design chain initiatives.

The work undertaken by Cadence and ARM should benefit all designers, not just Cadence customers, Kuo said. But he added that the same power savings cannot be guaranteed without the all-Cadence tool flow used by the initiative's members. The tools included RTL Compiler synthesis, CeltIC signal-integrity analysis, VoltageStorm power analysis and Encounter IC layout.

Cadence has automated the process for MSV design to make it practical for others to do, Kuo said. One MSV design challenge is translating voltages for the signals that interface between voltage domains. That is done by level shifters, special cells that perform voltage translation and clamp cells to provide isolation.

The ARM1136 core had 3,400 signals that went from 0.8V to 1V. Inserting 3,400 level shifters manually would have been a tedious process. Cadence and ARM automated the insertion of level shifters, hooking them up to power rails and optimizing placement for area and timing.

That required changes to both Cadence's IC implementation tools and the IP libraries provided by ARM, said Susan Runowicz-Smith, chair of the Silicon Design Chain Initiative steering committee and Cadence's marketing director for industry alliances.

The second major contribution, she said, was to design a single ECSM library that could be used for delay prediction across multiple voltage ranges. The ECSM models achieved delay prediction that correlated, on the average, to within 0.5 percent of SPICE, she said.

Dhurmil Gandhi, VP of product technology at ARM, confirmed that his company and Cadence jointly created level shifter cells that work with Cadence placement and routing tools, and ECSM models that allow timing analysis at different Vdd points. He said that ARM is also working with Synopsys Inc. and Magma Design Automation Inc. on low-power design.

- Richard Goering

EE Times

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