Voltage-mode control curbs power issues

The article takes a historical perspective on how component technology progress has shaped optimal voltage-mode control circuit selection. A practical set of rules and recommendations is provided for the synchronous buck converter using ceramic capacitors.

The overall frequency-response loop has two parts. The first includes a power-stage with driver and PWM comparator. The second is a Type 3 compensation circuit based on an error-amplifier with the R and C external components shaping the required feedback-loop frequency response. The Type 3 compensation circuit has two poles, with two zeros and a pole at its origin providing an integration function for better DC accuracy. Optimal selection of the compensation circuit depends on the power-stage frequency response. The theoretical small signal analysis and related equations for the buck converter can be found in the references.

To see how these technology achievements impact power-stage and feedback-loop design, consider a buck converter with the following characteristics: V_in = 12V, V_out = 5V, I_{out (max)} = 10A, I_{out (min)} = 0.5A, output ripple p-p.

The following conclusions can be made based on these comparisons:

? Modern ceramic capacitors allow using smaller capacitance and inductance for the output filter while providing the same peak-to-peak output ripple as the old technologies.

? The resonant frequency of the output filter is higher than before. Hence, the ratio between the converter's switching-frequency and the output filter's resonant frequency is lower—only 15.4 for the ceramic capacitors in this example.

? Lower-loss power stage results in low-damping, high-quality factor output filter.

? The output capacitor ESR-related zero frequency is in the MHz range and well above that of the resonant frequency.

Low-damping and high ESR-related zero frequency means almost 180 degrees phase-lag above the resonant frequency that should be compensated by the feedback loop; and

? Because of relatively low output capacitance, the converter with the ceramic capacitors requires high bandwidth and gain feedback loop for a better transient response.

Optimal circuit selection

The following rules are suggested for the voltage-mode control buck converter using ceramic output capacitors to enhance performance with a comfortable stability margin:

? Maximum valid frequency of averaged, small-signal switching converter model—If a modulator does not have the sampling delays, and only the driver delay and power FET switching delay are present, then the power stage and modulator small-signal transfer function is relatively accurate up to the half of the switching frequency.

? Limitation of widely used compensation circuit equation—Type 3 compensation circuit is preferred for its flexibility. Widely used equations are valid only if the error-amplifier bandwidth boundary is at least an order above the compensation circuit such as the R1, R3, R5, C6, C7 and C8 frequency response. Otherwise, use a more complex and accurate equation.

? Location of compensation poles—The ESR-related zero frequency is in the few MHz range and does not affect the phase lag at the resonant frequency. In this case, two equal poles in the HF region allow maximum bandwidth and gains to provide effective noise rejection at the switching frequency.

? Gain at the switching frequency—The output ripple of ceramic output capacitors is significantly less and has almost 90 degrees phase-lag vs. ripple of electrolytic-type capacitors in the same conditions. This allows the use of higher gain—up to 20dB to improve the transient response.

? Location of compensation zeros—Switching to a resonant-frequency ratio for the ceramic output capacitors can be as low as 15. If the crossover frequency is selected Fs/5, then the ratio between the crossover and resonant frequency is only three. The best strategy is locating the first zero two decades below selected equal poles for the maximum phase-boost. The location of second zero should provide an additional phase-boost to ensure 45 degrees phase margin at the crossover frequency and at least 30 degrees phase margin in the vicinity of resonant frequency to avoid a conditional instability.

? Impact of component tolerances on recommended phase margin—Unlike electrolytic, the modern ceramic capacitors with X5R and X7R dielectric are more thermally stable. The production tolerances are also in the ±20 percent or even ±10 percent range.

? The ESR-related zero frequency that varies in wide-range for the electrolytic capacitors do not impact the feedback loop design in case of ceramic capacitors. That means the overall feedback loop parameter variations are much less and the phase margin 45 degrees at nominal conditions can be used as a design goal to ensure the stability at the "worst case" conditions.

? Crossover frequency selection—Unlike the electrolytic, the converter with ceramic capacitors requires high bandwidth and gain feedback loop to match the speed of relatively-low inductance of the output filter. Because the ESR and ESL of ceramic capacitors are almost negligible in most cases, the speed of the feedback loop and output inductor along with the output capacitance C define the load current transient performance.

Based on the recommendations provided, the feedback-loop for the synchronous buck converter with ceramic output capacitors has been designed. As mentioned, two equal poles are located in HF region. This increases the gain with comfortable phase margin even with the use of relatively low, 5MHz bandwidth error amplifier available for this application.

- Rais Miftakhutdinov

Systems Engineer, Power Supply Control Products

Texas Instruments Inc.