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Mentor Graphics extends Catapult C synthesis product

Posted: 05 May 2005 ?? ?Print Version ?Bookmark and Share

Keywords:catapult c? synthesis algorithmic synthesis tool? electronic system level? design tool?

Mentor Graphics Corp. announced extensions to its Catapult C synthesis algorithmic synthesis tool, an electronic system level (ESL) design tool.

The extensions enable the Catapult C synthesis tool to create SystemC transaction-level models and wrappers, allowing designers to rapidly explore architectural tradeoffs and simulate their designs 20X to 100X faster than traditional register transfer level (RTL) using verification environments that support SystemC, like Mentor's ModelSim.

The Catapult C synthesis tool enables designers to use algorithmic C++ models as a "golden source." The tool employs interface synthesis and sequential-to-structural transformations to automatically generate SystemC or RTL hardware descriptions without changing the original sequential C++ source. Currently, Catapult C synthesis uses C++ to produce behavioral SystemC models that simulate 20-100X faster than RTL, with future releases intended to generate more abstract transaction-level SystemC models that simulate more than 1000x faster than RTL.

"The combination of algorithmic synthesis from pure ANSI C++ with an integrated SystemC verification environment provides a powerful solution for ESL design," said Simon Bloch, general manager of the Mentor Graphics design creation and synthesis division. "For the first time, designers now have a methodology for easily implementing a 'golden source' from the algorithmic level of abstraction down to technology-specific RTL. With the ability to generate SystemC models, designers can now rapidly explore architectural tradeoffs and verify their design, while re-using existing C++ and SystemC testbenches throughout the flow," Bloch added.





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