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Atrenta expands RTL analysis and verification

Posted: 09 May 2005 ?? ?Print Version ?Bookmark and Share

Keywords:atrenta? rtl analysis and verification? ic design? predictive development tool? 1team analyze?

Claiming new capabilities for IC design, Atrenta Inc. rolled out "predictive development" tools for RTL analysis and assertion-based verification last week.

The new tools, 1Team Analyze and 1Team Verify, complement the 1Team Implement tool suite that Atrenta launched in April. 1Team Implement is a unified physical planning, design and IC implementation solution that includes initial placement.

1Team Analyze is an enhanced and extended version of Atrenta's Spyglass analysis tool. What's new, said Simon Young, business unit director for Atrenta, are options for test and power analysis, along with a capability to not only analyze problems in RTL code but to fix them.

Using static and dynamic analysis, 1Team Analyze diagnoses structural, coding, and consistency problems in RTL code, and traces problems to their source. "We're not just checking RTL for style and consistency, we're checking it for design intent, which lint tools don't do," Young said said. "We're checking for power or test characteristics, or for the length and breadth of logic cones."

Optional power and test analysis options come with a capability called AutoFix, which can automatically make corrections to RTL code. For example, the tool can insert level shifters in the correct places for multiple power domains.

The test option, said Young, can produce a coverage analysis that correlates to about one percent with Synopsys' TetraMax or Mentor Graphics' FastScan automatic test pattern generation (ATPG) products. The AutoFix capability can correct clocking mistakes and ensure that registers are scannable.

1Team Verify, meanwhile, is an enhanced version of Atrenta's Periscope product, said Mani Narayan, product marketing manager at Atrenta. One major difference is that 1Team Verify automatically generates its own assertions, he said.

1Team Verify can generate assertions to cover clock-domain crossing, finite state machines, handshake mechanisms, and bus structures. Users can also write their own assertions using the Property Specification Language (PSL) or SystemVerilog, or bring in assertions from the open-source Open Verification Library (OVL).

The block-level tool reports whether assertions have passed or failed, and includes an integrated waveform viewer.

1Team Analyze and 1Team Verify will both be available in the third quarter, with prices starting at $45,000 and $80,000, respectively.

- Richard Goering

EE Times




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