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Mentor PSPs support LSI DSP cores

Posted: 10 May 2005 ?? ?Print Version ?Bookmark and Share

Keywords:mentor graphics? lsi logic? seamless? processor support package? psp?

Mentor Graphics Corp. and LSI Logic Corp. announced new Seamless processor support packages (PSPs) for the LSI Logic zsp400 and zsp500 digital signal processor (DSP) cores. Utilizing the Seamless PSPs with the ZSP cores, designers have a platform in which to concurrently develop hardware and software in complex SoCs, saving time and money, and validating that hardware and software are synchronized before prototypes are manufactured, said the press release.

"Seamless provides complete hardware/software co-verification coverage for SoC designers utilizing the ZSP cores. Seamless productivity enhancements enable customers to verify their system in a fraction of the time required by traditional RTL co-simulation approaches,&quot said Tuan Dao, VP and GM of ZSP Product Division, LSI Logic. &Quot;By easing the co-verification burden, Mentor Graphics allows our customers to achieve design closure quickly and correctly, enabling the successful deployment of ZSP-based products to the market."

The cost, power and performance optimization of the ZSP400 and ZSP500 cores make them suitable for software-intensive applications such as those in wireless, voice and multimedia. According to the two companies, the Seamless product provides designers of these emerging applications with unparalleled ability to debug hardware/software interactions while exercising production-level software running on the Seamless model of the ZSP core. The Seamless product's performance profiling capabilities provide accurate measurement of key design parameters, such as bus, memory and software performance, enabling users to evaluate system performance before committing to hardware.




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