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Verific Design licenses HDL component software to Calypto

Posted: 11 May 2005 ?? ?Print Version ?Bookmark and Share

Keywords:hardware description language? component software? hdl? C++?

Calypto Design Systems Inc. has licensed Verific Design Automation's hardware description language (HDL) component software.

Verific's HDL component software of C++ source code-based parsers, analyzers and elaborators for Verilog and VHDL serves as the standard front-end for Calypto's breakthrough SLEC functional verification software.

The SLEC product family is a sequential verification solution that proves functional equivalence between two IC designs that contain differences in levels of abstraction and sequential behavior. SLEC can compare functionality of designs written in any combination of VHDL, Verilog, SystemC or a C/C++ hardware description.

"The decision to work with Verific was an easy one for us because its HDL component software is the standard front-end source code," says Gagan Hasteer, Calypto's VP of engineering.





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