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TSMC expands DFM recommendations at 90nm

Posted: 11 May 2005 ?? ?Print Version ?Bookmark and Share

Keywords:design-for-manufacturing? 90nm?

Taiwan Semiconductor Mfg Co. Ltd is expanding its design-for-manufacturing recommendations for engineers working with 90nm design rules, company managers told the TSMC 2005 Technology Symposium here last week.

Six new guidelines, several of which were detailed here last week, build on those delivered at last year's symposium and extend to the 90nm platform of the world's largest foundry, said James Wang, who heads TSMC's design-for-manufacturing (DFM) program.

The "most important change," Wang said, is in metal deposition, which must be relatively uniform across a die to prevent dishing and other problems during the chemical-mechanical polishing steps.

"The dummy fill recommendations are the most important in the mass-production phase," said Wang. The new metal density rules include avoiding any metal-free area larger than 3 microns square. The DFM "recommendation" is to keep metal widths equal to or greater than 0.16 micron on top of an oxide area that is 5 microns square, while the DFM "rule" is 0.14 micron.

To accomplish a more uniform metal density, TSMC offers a utility that inserts dummy metal lines in areas that have low metal densities, Wang said.

In packaging, the company offers a power map evaluation tool to eliminate "hot spots," Wang said.

TSMC has developed a yield sensitivity analyzer utility that checks the vias, interconnect and poly opens and shorts, and other likely problems.

TSMC also offers a lithography process check (LPC) tool, a simulation-based environment that analyzes designs for patterns likely to result in yield problems. The LPC process links wafer and mask inspection tools to the LPC simulator.

TSMC has refined its optical proximity correction guidelines as well to ensure "predictable patterns" that yield well. Obeying the OPC-friendly guidelines can shorten mask-making cycle times by about 10 percent, Wang said.

"Highly proprietary details" are available on the company's password-protected "TSMC Online" Web site, which is accessible by customers, a TSMC spokesman said.

DFM can improve yields, but it also can result in slightly larger die sizes and, possibly, reduced performance. In response to a question from an engineer in the audience about providing for worst-case scenarios, Wang said, "We are trying to come up with a DFM scoring system so that designers know how to prioritize. We want to provide information about how much gain [in yields] they can expect, with designs that don't increase in area. All that is under way. What we know is that it is very design-dependent."

Ed Wan, senior director of design service marketing, told the audience that the EDA flow for TSMC's 65nm platform will "link so that DFM rules will apply." At the Design Automation Conference next month, TSMC will unveil version 6.0 of its EDA reference flow. By September, its 65nm DFM guidelines will be formalized.

Sally Liu, director of Spice modeling, said TSMC is "in the final stages of rolling out statistical modeling," with introduction likely in the second half. Also, by late this year or early next year, TSMC expects to support inductance modeling, she said.

The company is developing support for BSIM (Berkeley simulation) 4.2 and BSIM 4.3 models, said Liu, who holds a doctorate from the University of California at Berkeley, where the Spice models were developed.

Power management is the key challenge facing nanometer-level designs, and Liu said models must better reflect the three main sources of leakage current: gate leakage; reverse diode leakage, particularly when reverse body bias techniques are employed; and surface channel leakage, which depends in part on temperature.

Kenneth Kin, senior vice president of worldwide sales and services, said TSMC is offering to develop processes specific to customers or applications. Those processes would be custom, rather than tweaks of a standard process recipe.

"In the past, we developed one-size-fits-all technology," said Kin. "We developed the process technology, and Mr. Customer did the design. Now, we would like to develop technologies specifically for customers or applications. Working together, we can look at your application and add options or strip down layers that are not necessary."

- David Lammers

EE Times

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