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Tackling RF, mixed-signal integration

Posted: 16 May 2005 ?? ?Print Version ?Bookmark and Share

Keywords:rf? wireless? mixed-signal? integration? transmitter?

Historically, cellphones have used superheterodyne receivers and transmitters. With the growing demand for multimode terminals encompassing multiple standards such as GSM, cdma2000 and W-CDMA, however, direct-conversion receiver and transmitter architectures have become popular. IC technology has made such tremendous progress in the last decade that it has become possible to integrate varied RF, mixed-signal and baseband processing on a single chip.

A typical cellular transceiver encompasses the RF front-end, the mixed-signal content and the actual baseband processing. In the case of receivers, common architecture choices are direct conversion to DC, very low IF and direct sampling. But direct conversion to DC suffers from DC offset and LF noise. While low IF alleviates this, image rejection is a key challenge. And direct sampling at RF has its own obstaclesLF noise, aliasing from wideband signals and dynamic range requirements.

In all those architectures, however, the key challenges are the integration of analog and digital functionality. Once the signal is downconverted to DC or a very low IF, there is the wanted signal, along with unwanted blockers that are significantly higher than the signal. Digitizing that combination of signals requires a high-dynamic-range adc with excellent noise and spurious-free dynamic range performance. For example, in the case of global system for mobile communications (GSM), the blocker at 3MHz offset from the carrier is 76dB above the signal, while the blocker at 600kHz offset is 56dB above the signal. This sets the upper limit of the ADC.

Further, at reference sensitivity level, the wanted signal at the A/D input would be 1mV (-60dBV). Since the quantization noise floor must be low enough not to degrade the noise-figure performance, the noise floor required would be -80dBV (for a 1mV signal). Meanwhile, CDMA and W-CDMA have much lower SNR requirements, so the tolerable quantization noise floor is relaxed correspondingly.

The choice of high-dynamic-range sigma-delta converters can range from continuous-time to discrete-sampled-time converters. The continuous-time ADCs offer the advantage of an anti-aliasing filter that can be embedded as a part of the converter. On the other hand, discrete-time converters need an anti-aliasing filter before the converter to eliminate spectral images.

The order of the modulator is another design parameter that affects dynamic range. Higher-order modulators result in increased dynamic range, but can suffer from potential stability problems. Single-bit quantizer vs. multibit quantizer also affects dynamic-range performance. Each additional bit provides 6dB of dynamic range, but this topology needs mismatch shaping in the feedback path to achieve the required dynamic range.

Digitization at an early stage after the antenna has its advantages in terms of robust design and lower costs. Wide tolerances in analog components are eliminated, and digital processes of the digital blocks can be geometry-shrunk, thus reducing chip size and corresponding costs. That also leads to true software-defined radio architectures, where the ADCs and the digital back-end can be switched to accommodate standards such as CDMA, W-CDMA and GSM. Newer requirements for multimode radios, such as simultaneous operation of W-CDMA and GSM for intersystem handoffs, diversity reception for enhanced capacity and Bluetooth functionality must be considered in architectural choices. Simultaneous operation of multiple standards does not allow reuse of functional blocks and potentially results in increased die size and power.

The high-dynamic-range A/D is clocked by a high-speed sampling clock, so substrate noise and coupling to the RF front-end must be considered carefully in the design and layout. Interference from the harmonics of the sampling clock at RF can degrade the performance of the receiver if it falls within the channel bandwidth. Once the signal is digitized, a common hardware platform can be used to extract the wanted signal while rejecting the blockers. Several radio functions, such as DC offset cancellation, AGC and frequency offset correction, can be performed as part of the radio before actual data demodulation. That reduces the MIPS requirement of the DSP while allowing more flexibility in radio control.

Tx designs

Transmitter architectures for multiple standards include direct upconversion, translation loop, modulation through PLL and polar loop. The trend has been toward further digitizing to reduce the analog content in the total transmitter chain. Key challenges include current drain, dynamic-range requirements and cost. Loop-phase modulation using a sigma-delta modulator shows promise in terms of low-power consumption and a simpler architectural approach.

For systems like CDMA and W-CDMA, separation of AM and PM components is required. That leads to polar-loop architectures, which are gaining wider use. But challenges remain in their use for wideband systems, where alignment of the AM and PM components and the effect on spectral distortion are critical.

While direct modulation has the advantage of compatibility with multiple standards, the challenges of meeting noise-floor requirements remain. Multimode phones require several bulky SAW filters to attenuate the receive band noise.

Signal digitization in the transmitter could include I and Q oversampled DACs to ease the requirements of the reconstruction filter. Since there are no blockers in the transmitter, this somewhat eases the design of the converter. Sufficient dynamic range to meet spectral mask requirements still has to be considered in the transmitter chain.

The final stage in the transmitter chain is the power amplifier, which transmits close to 3W at maximum output power in certain systems. Maintaining efficiency at such power is critical; traditionally, power amplifiers have been designed in GaAs or InGaP.

Recent trends point toward CMOS power amplifiers that can potentially enable on-chip integration with the rest of the transmitter and lower system costs. However, challenges remain in terms of efficiency, thermal behavior and isolation.

Avarind Loke, Sr. Director

Bala Ramachandran, Systems Principal Engineer

Skyworks Solutions Inc.

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