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Samsung prepares in-house EDA tools to link design, process

Posted: 17 May 2005 ?? ?Print Version ?Bookmark and Share

Keywords:eda tool? semiconductor circuit design? soc? driver ic? cmos image sensor?

Samsung Electronics Co. Ltd has chosen to develop two diagnostic EDA tools in-house and it estimated their application would save the company $30 million in development costs each year.

The software tools, called Escort (Estimation of Chip Performance on Process Tolerance) and SRSIM (Samsung Reliability Simulator) assess a semiconductor circuit design for potential errors in the preliminary design stage, Samsung said.

The Escort software can increase wafer yields while SRSIM can estimate when the performance of transistors in memory chip circuits might deteriorate in production after a series of designated time-lapses.

The software would be used to reinforce the production of memory products and reduce development time and costs, Samsung said, although the diagnostic processes could also be applied to display driver ICs, CMOS image sensors and system on chip (SoC) designs, Samsung added.

By improving product yield and eliminating correction on mask, the Escort/SRSIM combination is expected to shorten product development by at least four weeks. Based on the reduced design time and increased wafer yields, it is projected the software will save Samsung $30 million in development costs each year.

- Peter Clarke

EE Times





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