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Philips Semiconductor CTO outlines system-in-package challenges

Posted: 17 May 2005 ?? ?Print Version ?Bookmark and Share

Keywords:system-in-package? sip? eda tool? cmos?

The next step forward in integration has to address system-in-package (SIP) issues and needs EDA tools with broader scope and greater standardization of approach, according to Rene Penning de Vries, chief technology officer of Philips Semiconductors.

During keynote speech given to a two-day conference organized by the Fabless Semiconductor Association and the Institution of Electrical Engineers here, Penning de Vries presented a philosophy based on "More Moore" and "More than Moore".

More Moore is the increased monolithic integration predicted by Gordon Moore's infamous law of increasing complexity, now elaborated in the International Technology Roadmap for Semiconductors (ITRS). However, this progress would be reserved for the basic CMOS system-on-chip and pre-dominantly cover the digital domain, Penning de Vries said. The true system approach - the More than Moore part - would be catered for by a multi-die package; a template that includes the digital SoC together with wireless, sensor and actuator die as necessary, he added.

SIP is already proving successful in the realm of memory components for mobile handsets where under the term multi-chip package, or MCP, it has become a multi-billion dollar part of the global memory business. But assembling high-yielding memory die into a SIP is relatively simple compared with a assembling a generic logic-based SIP.

SO although the direction of development may now seem clear to the Philips executive there are challenges ahead, particularly in EDA, he said.

"Moore's Law has led to the ITRS. That does not exist in the SIP world," he told the keynote audience. "EDA tools do not exist in the SIP world. We need to use the tools in a common environment. We need to simulate not just the logic, but also the mechanical part of the design, the thermal part, and new packaging is required for new device types, such as for bio-chips."

In an interview with EE Times immediately before giving his keynote Penning de Vries said that it was clear that Philips' Nexperia platform approach to design would now have to step up to the SIP level.

He said that although EDA companies often focused on aspects of monolithic integration companies such as Cadence were responding to Philips' call for SIP support.

"Cadence: they are responding. Or do we approach this from the PCB level? The PCB tools exist. Can they be adapted to take in the complete picture? We are working on that. But in the end commercial EDA tools are about productivity. There's always a way to get what we want done. There's always a way out. There are separate tools and so on. But we need them in a common environment."

Such calls to EDA companies for integrated multidisciplinary design have come in the past, from OEMs such as automotive manufacturers, and largely gone unanswered.

"EDA for SoC is evolution. EDA for SiP is almost a new paradigm. The heterogeneity is huge so we do need to focus and then attack with a set of integrated tools that cover, electrical, logical, mechanical and thermal performance," Penning de Vries said.

In a response to a question at the end of his keynote, Penning de Vries admitted that self-discipline in limiting the SIP options and a standard-setting successful component in the SIP world would likely be important to the speed of adoption of SIP.

- Peter Clarke

EE Times





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