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How FPGA packaging drives signal integrity

Posted: 25 May 2005 ?? ?Print Version ?Bookmark and Share

Keywords:fpga? signal integrity? package?

By Panch Chandrasekaran

Xilinx Inc.

Until recently, signal integrity has been a concern relegated predominantly to multi-gigabit serial interface design. Today, it is an aspect of design that engineers building high-speed parallel interfaces like memory interfaces can no longer choose to ignore.

As speeds increase, bit periods shrink, reducing the available timing margins. Today's memory interfaces run at greater than 500Mbps per line with rise times in the hundreds of picoseconds. This creates a substantial signal integrity challenge for the FPGA designer.

As interfaces get wider and faster, simultaneously switching output noise (SSN) grows in severity. SSN adds to the system jitter, eating into the timing margin and affecting system performance. In the worst case, SSN can cross the logic threshold, causing the system to malfunction altogether.

Good package design is critical to good noise performance in FPGAs. This article describes the package design considerations with a focus on signal integrity and its impact on system performance.

The role of the package

Historically, short signal paths have not altered signal characteristics because speeds were still fairly low. Today, with rise times in the hundreds of picoseconds (even if bit periods are few nanoseconds), the frequency components of signals run into GHz, causing even very short signal paths like package traces to impact signals.

For every signal line there is an associated return path for the return currents. For single-ended signals, these return paths are usually GND or VCC reference planes. To maintain a 50-ohm line the returns should be in close proximity to the signal.

While PCB traces are less of a concern, designers must pay close attention to vias. For large FPGAs the breakout regionthe area between the package balls to the PCBis extremely critical since it comprises a dense concentration of signal vias.

SSN is generally observed as "ground bounce" and can be caused by two different phenomena:

Package and PCB via-field crosstalk. Noise due to via-field crosstalk is a function of the loop inductance, which is a function of the proximity of ground/power reference pin locations to the signal pin. Signal pins that are farther away from a reference pin are more susceptible to noise.

This problem is exacerbated when a number of I/Os in the region switch simultaneously. Hence proper distribution of ground/power and signal pins in a package is extremely criticalin other words, a good pinout architecture.

Compromised power integrity due to high package inductance. Maintaining a clean power supply to the FPGA is critical to maintain acceptable signal integrity. Noise margins are reduced as VCC values drop down to 1.2v in the latest FPGAs.

Further, any noise in the power rail translates to jitter at the output, shrinking the available timing margins as well. As noise depends on package inductance and number of simultaneously switching I/Os (L.di/dt), optimal signaling requires a good low-inductance package.

Tackling the SSN challenge

One package that tackles the SSN challenge is the Xilinx Virtex-4 FPGA package with the SparseChevron Pinout Architecture. Most notably, the package enables better noise performance on higher-speed, single-ended interfaces which are more susceptible to noise than differential interfaces such as LVDS.

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