Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Embedded

Multiple-processor VME boards serve air-cooled MIL apps

Posted: 27 May 2005 ?? ?Print Version ?Bookmark and Share

Keywords:military embedded electronics? mercury computer systems? race++? vme boar?

As the press announcement implies when it refers to the Military Embedded Electronics and Computer Conference, these products from Mercury Computer Systems are primarily slated for high-end military applications. As such, they meet MIL specs.

Okay, so what will the RACE++ series ruggedized board-level products do? As conduction-cooled VME boards, they give you the ability to physically position high-performance signal processing, for applications such as imaging and radar, alongside a system's sensors?and do it without substantial air flow. No blowers. No fans. No noise. No dust and dirt.

These boards are very powerful. Each packs no less than four PowerPC processors, dishing up more than 25 GFLOPS (floating point operations per second) before scaling up by means of crossbar switching.

As the company's press release notes, the power of these boards also rests largely on the so-called CNs or compute nodes. The CNs pack the Mercury-designed CN interface chip. It's what enables concurrency between the system's arithmetic and I/O operations.

Each PowerPC 7447A-equipped CN includes a pipelined on-chip L2 (Level 2) cache, with 32KB for instructions and 32KB for data). It's largely what's responsible for the 32 bytes/clock cycle performance to L1 cache. This high-performance cache subsystem gives rapid access to data previously loaded from memory, but too large to fit into the on-chip cache.

Memory controller, network interfaceThe CN interface also acts as both a memory controller and a network interface to the RACE++ switch fabric interconnect. The CN interface includes an enhanced DMA (direct memory access) controller (more on it in a moment), a memory system with error checking and correction, metering logic, and a RACE++ interface. Mercury claims that by integrating memory control and the network interface, the CN provides function and performance that wouldn't otherwise be achievable with separate components.

As with most high-performance system, much of the 7447A Multicomputer's performance also accrues to its memory system. The MPX bus used on the 7447A's daughtercard delivers memory access and sustained throughput enhancements over buses used on earlier daughtercards. In fact, Mercury claims that its memory subsystem permits the memory to approach the theoretical limits of its performance capability.

That claim is based on the use of 133MHz DDR-266 (double data-rate) DRAM. The DDR DRAM provides the bandwidth to handle overlapping local processor access and remote accesses over the RACE++ switch fabric.

Virtual mapping
Virtual mapping registers then provide fine granularity of address mapping, and the ability to simultaneously map connections to shared memory buffers on every node in a system. Beyond that, FIFO buffers overlap accesses to SDRAM from the local processor and Mercury's RACEway interconnect. Board-to-board RACE++ communication takes place through the RACEway interlink modules.

The interlink modules form the backbone of a RACEway high-bandwidth switch fabric. In use, RACEway supports multiple high-speed data transfers simultaneously by providing multiple pathways between network nodes. Six-slot, 8-slot, 12-slot, and 18-slot dual-port modules are available for use in these multicomputers. Each dual-port RACEway interlink supports 533MBps transfers per slot.

The architecture also includes memory error management. Each CN contains error-correcting circuitry to ensure data integrity. Single-bit errors are corrected; double-bit errors generate an error interrupt.

Super-Fast DMA
The DMA controller is a key element of the RACE++ configuration that supports RACEway transfers at 267MBps. With chained DMA, the DMA controller works from a linked list in memory, so that a complex chain of DMA requests requires no overhead from remote processors.

DMA requests also support non-sequential access to and from local memory. This so-called strided-DMA capability enables sub-matrix transfers as required for distributed 2D applications as found in image processing or synthetic aperture radar, for example.

The press release also notes mention the system's FPDP (Front Panel Data Port) capability. FPDP I/O is enabled using Mercury's conduction-cooled RINOJ-T daughtercards. Implementing the FPDP protocol, the cards are capable of 160-Mbyte/s sustained parallel TTL input or output.

The cards provide 16k x 36bit FIFOs, and use DMA to accelerate data movement without incurring processing penalties. Finally, the daughtercards support all four FPDP modes: unframed, single-frame, dynamic size repeating frame, and fixed-size repeating frame. The RINOJ-Ts also implement data-directed DMA. It can react to sensor-mode changes without processor intervention. Moreover, the RINOJ-Ts are compatible with more than a hundred FPDP products.

Software support
The press release briefly mentions that the RACE++ family is supported by RACE++ software for both development and deployment. As you'd expect with a product like this, that's an understatement.

For starters, Mercury Computer Systems provides a common software environment. Shared components include a MCOE (multicomputer operating environment), a SAL (scientific algorithm library), and a PAS (parallel acceleration system) communication library.

The MCOE imparts a deterministic realtime multiple-computer platform. The SAL provides a method of accessing the power of the AltiVec vector unit. SAL contains hundreds of image and signal processing functions optimized for AltiVec.

For its part, the PAS supports the DRI (Data Reorganization Interface) standard. That gives you a variety of scalable multiprocessor communication patterns, using high-level library calls. Once programmed in PAS, an application can scale to a larger or smaller number of CNs. All you need do is change run-time variables.

Integrated development environment
These conduction-cooled products also share a RACE++ IDE (integrated development environment). It includes Green Hills's MULTI IDE, Mercury's TATL (trace analysis tool), and the Supervisor multiprocessor monitoring tool. The compiler tool chain works with the debugging and analysis tools. Mercury also offers C and C++ compilers.

-Alex Mendelsohn

Article Comments - Multiple-processor VME boards serve ...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top