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EDA vendors announce flows for IBM-Chartered 90nm process

Posted: 27 May 2005 ?? ?Print Version ?Bookmark and Share

Keywords:eda? pci express? rtl-to-gdsii? encounter rtl compiler synthesis? soc encounter global physical synthesis?

IBM and Chartered Semiconductor Mfg added common design support to their jointly developed 90nm process platform.

The support includes power-optimized, manufacturing-aware libraries, low-power EDA reference flows and design kits for critical high-speed connectivity interface standards, including USB 2.0 and PCI Express, the companies said.

IBM and Chartered said ARM, Cadence Design Systems Inc., Magma Design Automation Inc. and Synopsys Inc would provide support for the process. Cadence, Magma and Synopsys immediately announced reference flows to support the process, each of which uses ARM's Artisan Metro low-power libraries for flow development.

Cadence said its low-power, RTL-to-GDSII reference flow would be based on its Encounter(TM) digital IC platform and incorporate the company's Encounter RTL compiler synthesis, SoC Encounter Global Physical Synthesis, VoltageStorm dynamic gate power rail analysis and CeltIC nanometer delay calculator.

Synopsys said its Galaxy design and Discovery verification platforms would serve as the foundation of its IBM-Chartered 90 nm low-power reference flow.

Magma said its flow leverages Blast Power and Blast Rail NX in addition to Magma's IC implementation products.

- Dylan McGrath

EE Times

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