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Choosing the right interconnect

Posted: 01 Jun 2005 ?? ?Print Version ?Bookmark and Share

Keywords:ttl? ecl? cmos? oem? i/o?

Ritchey: Today, CMOS is the technology of choice and it is common for CMOS chips to have rise times well below half a nanosecond and clock speeds well above a gigahertz.

The march of technology has made it important for all digital designers and component suppliers to use the same skills that were once only required of supercomputer engineers such as those of Cray Inc. and IBM Corp. and their suppliers.

In 1980, the rise and fall time of TTL components was in the 15ns range, while the ECL used in supercomputers was in the range of half a nanosecond. TTL-based designs were clocked at 10MHz, while ECL computers were clocked at 100MHz and higher.

Fast forward to 2005, TTL has gone away and ECL has essentially disappeared. Today, CMOS is the technology of choice and it is common for CMOS chips to have rise times well below half a nanosecond and clock speeds well above a gigahertz. Thus, every engineer and component supplier is now in the supercomputer business.

Despite the fast speed of these CMOS devices, their corresponding package designs and application notes are still being done using the guidelines that worked for TTL speeds. As a result, many ICs don't work as expected.

Clearly, design engineers depend on IC manufacturers to create products that perform as specified and bet their designs on them, much as the designers of the Golden Gate Bridge depended on the makers of the wire in the cables to make sure the wire was strong enough to do the job. Here is my wish list of the steps I think IC manufacturers should take and the information they should provide systems makers:

? Accurately characterize each I/O so OEMs know exactly how it works;

? Provide accurate models (spice: Modeling languages for the demanding EDA industry" target=_blank>ibis and SPICE) so OEMs can properly perform signal-integrity analysis;

? Design IC packages with sufficient care so that all circuits work properly without interfering with each other;

? Provide 3D models of the IC packages so OEMs can include them in the signal-integrity analysis;

? Use the actual parts in real circuits before preparing application notes;

? Write application notes based on the part being described and support each design rule with proper engineering analysis.

Unfortunately, chipmakers don't always follow all of these steps, and that leads to a host of problems.

When packages are not properly designed, two major types of failure occur. First, there can be noise on Vdd and ground inside the package resulting from many single-ended outputs switching simultaneously. There can also be coupling of noise from one signal to another inside the package.

Both of those problems are the result of excessively large amounts of parasitic inductance in the power paths of IC packages. This is a parameter that cannot be controlled by the design engineer. It is in the hands of the IC manufacturer. Designs with these kinds of problems can only be fixed by changing the IC package.

One way to combat shortcomings is to ask an IC supplier for the following during the selection process: a complete list of package parasitics, models of the I/O to use in simulation and examples of real functioning circuits. You should also obtain a set of application notes with supporting engineering analysis to demonstrate that the design rules are robust.

- Lee Ritchey

President

Speeding Edge





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