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Mentor IP core selected by China's primary research center

Posted: 02 Jun 2005 ?? ?Print Version ?Bookmark and Share

Keywords:microprocessor development and research center? i/o architecture? pci express ip?

The IP core based on the PCI Express architecture from Mentor Graphics Corp. has been selected by the Microprocessor Development and Research Center (MPRC) of Peking University in China. The PCI Express IP was chosen based on its configurability and performance of root, switch and endpoint applications. It will be used for next-generation I/O architecture of MPRC's microprocessor technology.

MPRC serves as China's primary research center for computer science, technology and microelectronics and it has established a joint laboratory with Mentor Graphics for system-on-chip (SoC) verification, chip prototyping and hardware-software debugging. The joint laboratory also supports IP applications for chip design, which is why MPRC selected Mentor Graphics' IP for the PCI Express standard.

Using compliant IP for the PCI Express standard enables design engineers to focus on the differentiating aspects of their design and accelerate design time with highly configurable, reusable, low-cost IP building blocks to create innovative electronic systems. Mentor recently announced that its configurable port for the PCI Express specification met compliance by the PCI-SIG organization.

According to Mentor, the synthesizable core implements the PCI Express specifications in a configurable block that provides transaction layer, data link layer, and media access controller (MAC) functionality down to the physical layer interface (PHY) for the PCI Express interface (PIPE). For added flexibility, the core can implement L1 and L2 features of the ASI specification and there is an option of operation either as a root or as an endpoint with the choice made at boot time.





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