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New floating-point and DVB-S2 cores strengthen DSP IP library

Posted: 02 Jun 2005 ?? ?Print Version ?Bookmark and Share

Keywords:xilinx? digital signal processing? dsp? ip library? virtex-4?

Xilinx Inc. has updated its digital signal processing (DSP) IP library for its Virtex-4 and spartan-3e field programmable gate array (fpga) families to include a suite of floating-point operators and a digital video broadcasting (DVB) satellite FEC encoder core.

Developed in conjunction with Qinetiq, the floating-point LogiCORE module delivers tens of giga floating-point operations per second (GFLOPS) and supports processing requirements in advanced communication and radar systems. The new core, which is included with Xilinx ISE software, enables customers to reduce component count and system cost by performing the floating-point arithmetic using the FPGA.

The latest encoder core performs FEC in DVB satellite version 2 (DVB-S2) systems based on concatenation of Bose-Chaudhuri-Hochquenghen (BCH) with low-density parity check (LDPC). The inner coding brings the performance at times only 0.7dB from the Shannon limit, providing an encoding output rate of about 700Mbps using Virtex-4 devices.

"The release of the new floating-point operator library supports customers developing advanced communication systems in the broadband, 4G, beyond 3G (B3G) and JTRS space. These operators are key functions required for delivering numerically robust implementations of QR-decompositions (QRD) matrix inversion, singular value decomposition and Cholesky factorization for beam forming and MIMO processing," said Dr. Chris Dick, chief DSP scientist at Xilinx. "Parallel configurations of the new operators in our Virtex-4 device technology delivers the high-performance required in advanced wireless systems in a cost effective manner."

Xilinx also made key enhancements to existing cores, including Turbo Covolutional decoder UMTS/3GPP, Reed Solomon decoder, Reed Solomon encoder, Viterbi decoder, direct digital synthesizer, MAC FIR filter, complex multiplier core and multiplier accumulator. Enhancements to these cores include full support for the latest ISE 7.1i development tool.

The floating-point operator is included with the latest version of the Xilinx CORE Generator system. For a limited time, customers can use the floating-point operator IP at no cost. The standard list price for the floating-point operator IP is $995. The DVB-S2 FEC encoder core is available as separately licensed parameterized netlists. The license price for the DVB-S2 FEC encoder core is $1,000.

- Ismini Scouras

eeProductCenter



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