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Tool brings power analysis to virtual-prototyping phase

Posted: 02 Jun 2005 ?? ?Print Version ?Bookmark and Share

Keywords:ic virtual-prototyping phase? silicon dimensions? chip2nite? design-planning tool? tool?

Bringing power analysis into the IC virtual-prototyping phase, Silicon Dimensions Inc. will announce this week the latest version of Chip2Nite, a design-planning tool aimed at logic designers.

In addition to a power density analysis, Chip2Nite version 2.3 adds an ability to generate custom wire-load models and a new "predictive" floor plan capability that doesn't require a manual pin assignment. Initially introduced in February 2004, Chip2Nite provides floor planning, placement, analysis and optimization to enable block-level design planning.

Michael Naum, Silicon Dimensions' president and CTO, said that Chip2Nite customers were looking for an easy way to do power density analysis. Most existing power analysis tools, he said, either address IC physical design or are further upstream in the RTL design phase.

"We don't have that many tools in the prototype stage in the hands of designers," he said.

To use the new capability, chip designers get an initial floor plan and placement, and then obtain switching-activity information from Synopsys Activity Interchange.

Format files generated during simulation. A placed DEF file is used for cell topology information, the Liberty library is used for cell pin capacitance information and Chip2Nite's router calculates individual wire capacitance for each route.

The output is a thermal map pinpointing density problems, along with a report on every instance in the design and its power consumption. This information is then passed to the physical-design team, which may decide to beef up its power mesh in critical areas.

"People are overdesigning power meshes," Naum said. "They have no idea what the activity-based power consumption looks like. They're leaving a lot of die size on the table by doing that."

The custom wire-load models generated by Chip2Nite 2.3, Naum said, are similar to those generated by back-end tools. But the process is a lot faster. "The feedback we've gotten from a number of customers is that it takes too long to get a custom wire-load model from the physical-design team," he said.

To generate custom wire-load models, users run placement in Chip2Nite and run the tool's virtual router. From this, Naum said, they know the fanout and net capacitances of everything in the design. "We do some polynomial curve fitting on that data and generate the wire-load models," he said.

The tool provides what the company calls a "physically aware pin-assignment" utility. It can determine where pins should go around the periphery of blocks, making manual pin assignments unnecessary, Naum said. "You just draw the bounding box of the chip and let it loose." Users can still manually assign or import pin locations, as before, but the new capability provides a higher level of abstraction, he said. "We've got users who want to do a level of floor planning who don't care how the block fits into the chip. They just want feedback right away."

Chip2Nite 2.3 will ship in late June on Linux platforms, starting at $25,000 for a one-year subscription.

- Richard Goering

EE Times

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