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Intel, Xilinx sponsors FPGA design tilt

Posted: 07 Jun 2005 ?? ?Print Version ?Bookmark and Share

Keywords:programmable logic? fpga?

Aiming to bolster the programmable logic technical know-how of engineering students, Intel Corp. through its Intel Innovation in Education program, and Xilinx Inc. have sponsored an FPGA-based design competition for university students in the Philippines.

Organized by the University of the Philippines Electrical and Electronics Engineering (UP EEE) department and the Advanced Science and Technology Institute (ASTI) of the Department of Science and Technology (DOST), the FPGA design tilt is intended to promote the competency of electronics engineering students in the design and implementation of electronic systems, specifically in utilizing FPGAs and hardware description language (HDL) for digital devices.

Rowena Cristina Guevara, dean of the College of Engineering in UP, said that an FPGA-based design competition impact the country's semiconductor industry. She explained that the country is currently doing low value-added activities such as manufacturing and assembly, and it's high time to get into design.

"If a product costs $100, the amount of money that goes to the manufacturer, which are the activities done in the Philippines, will only be $10. Whereas if you do design and testing, you'll get $40. Therefore it is important for our country to get into that design space," remarked Guevara.

Guevara expressed gratitude toward Intel and Xilinx for sponsoring the event because of its impact on the schools that would be doing FPGA design. She said that it is very important to get into the design space in a short amount of time because China and Vietnam are already going into the manufacturing space.

Mechanics

Participants in the competition will consist of teams comprising of up to three students currently taking up electrical engineering, electronics and communications engineering, computer engineering, applied physics and other related teams.

The challenge for this year's match is to develop a digital voice recorder with basic functionalities such as record, stop and replay with an FPGA starter kit. A 200Kgate Xilinx Spartan-3 FPGA starter kit with 12 18bit multiplier, 216Kb of RAM and up to 500MHz internal clock speed, as well as an analog I/O board comprising of microphone, pre-amplifier, A/D and D/A ports, audio power amplifier and speakers are provided to the participants of the competition.

Yvonne Flores of Intel Education Philippines stated that Intel is serious about its education-related activities by promoting the development of world-class curriculum through helping the universities in specific areas such as VLSI, material science and failure analysis.

Flores said that they are looking for faculty members and students who want to work on researches supported by Intel. One of the earliest projects supported were the fabrication run for IC researches in an Intel-sponsored laboratory at the University of the Philippines costing $17,000 per run, at two to three runs per year. She also announced the coming Asia academic forum which will gather between top professors that they have been working with from China, India, Malaysia, Taiwan and the Philippines, and Intel fellows.

Designs will be implemented in FPGA and will be based on Verilog or VHDL using only the IEEE standard library on the tools provided. The codec block of the design specification requires the participants to implement a dialogic ADPCM algorithm.

Prior to the contest, a training on FPGA-based design using VHDL was conducted by the microelectronics division of ASTI to the participants of the design competition.

"UP EEE and ASTI see the great importance of using HDLs and PLDs to implement complex digital systems," commented Marc Rosales, a faculty member at the EEE department. He said that the competition would help the country in generating highly-competent engineers geared towards engineering design activities.

Entries in the design contest would be judged based on the engineering design soundness, taking into consideration the tradeoffs and ingenuity at various aspects of the design. A chunk of the criteria would also be based on the clarity of the functional specs, system description and the HDL implementation, as well as the development of a thorough test methodology for the device.

Winners will take home cash prizes as well as a copy of the Xilinx ISE Foundation PLD design environment software. Contestants are required to present the project updates on August 2005, while the entries will be presented and judged on October 2005.

- Reden Mateo

Electronics Engineering Times- Asia





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