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Synopsys enhances DesignWare with SATA addition

Posted: 08 Jun 2005 ?? ?Print Version ?Bookmark and Share

Keywords:serial ata? verification intellectual property? designware library? interconnect?

Synopsys Inc. has added Serial ATA (SATA) verification intellectual property (VIP) to its DesignWare Library. SATA is an internal storage interconnect for connecting the host system to peripherals such as hard drives, optical drives and removable magnetic media devices. SoC designers now have access to SATA VIP to verify both 1.5Gbps and 3.0Gbps generations of the SATA standard with direct and constrained random verification methods at the block and chip level.

The Synopsys' SATA VIP includes device controller and monitor models for verifying designs with a SATA host controller interface. In addition to supporting third-party VHDL, Verilog and SystemVerilog simulators, DesignWare SATA VIP also supports Synopsys' VCS simulator native testbench (NTB) capability for improved runtime performance, as well as Synopsys' Reference Verification Methodology (RVM) with coverage-driven verification capability for improved productivity.

"Verification at block and chip level is a key concern for SoC designers using the SATA interface," said Guri Stark, VP of marketing, Synopsys' solutions group. "DesignWare SATA VIP, with advanced verification capabilities that include Native Testbench, Reference Verification Methodology with coverage-driven verification, gives SoC designers the ability to rigorously verify the SATA interface," added Stark.





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