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Celoxica ESL design suite upgrade expands speed, size limits

Posted: 13 Jun 2005 ?? ?Print Version ?Bookmark and Share

Keywords:electronic system level design? esl design? synthesis tool? fpga? dk4?

If you wield C-based electronic system level (ESL) design and synthesis tools to craft your circuits in FPGAs, you will appreciate DK4, the fourth generation of celoxica's dk design suite. For one thing, the suite introduces vhdl and Verilog optimizations that work with Design Compiler from Synopsys Inc. It also allows automatic scripting for generating SoC test benches, bridging the gap between an ESL software and the latest SoC physical design and verification flows.

In addition, DK4 offers advanced utilization technology that increases design capacity and speeds synthesis by 30 to 50 percent over previous versions, while synthesis optimization improves the quality of results. Other enhancements ease the move from software to silicon, linking ESL to physical SoC designs.

Generating optimized EDIF FPGA netlists from high-level descriptions, DK family members turn software into silicon. But rather than being limited to single block, single-clock modules, DK4 can synthesize complete systems, including complex algorithms, system interfaces and multiple clock domains.

A new GUI offers intuitive and easy-to-use design flow for all popular FPGAs. For example, the new tools help you exploit the embedded ALU features and DSP blocks found in very high-density FPGAs like Stratix II and Virtex 4. Specifically, DK4 covers the latest Xilinx FPGAs and high-density Spartan 3E and low-power Spartan 3L devices.

In addition, the latest suite improves technology mapping and, therefore, design quality of results.

DK4 runs under Windows and Linux operating systems.

Version 4 of Celoxica's DK Design Suite will be available next month (July). List prices range from $10,000 to $80,000, depending on the package options.

- Gil Bassak


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