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Enhanced tool set reconfigures FPGAs while system operates

Posted: 15 Jun 2005 ?? ?Print Version ?Bookmark and Share

Keywords:transparent field reconfiguration? transfr? latticexp? nonvolatile field-programmable gate array? lattice semiconductor?

Enhanced tool set reconfigures FPGAs while system operates

Programming software supporting Transparent Field Reconfiguration (TransFR) technology, which allows designers to reconfigure LatticeXP nonvolatile field-programmable gate arrays (FPGAs) in the field without interrupting system operation, is available at no charge from Lattice Semiconductor Corp.

The ispVM software is a Windows-based tool set, which generates C code that when compiled for and executed on embedded processors, enables the programming of Lattice devices.

Field logic reconfiguration can be achieved in two stages using the ispVM software. First, a 'background' programming command loads new data in flash memory of the Lattice XP device transparently without stopping FPGA operation. Second, device operation can be briefly suspended while an 'Xflash TransFR' command updates the SRAM from the flash block in approximately 1 millisecond.

This update can occur while holding the I/Os in user-defined states to avoid disturbing the surrounding system's operation. The ispVM software can either issue the commands directly through a programming cable during prototyping, or generate an industry-standard serial vector format (SVF) file for reconfiguration in the field.

"Field FPGA reconfiguration, driven by bug fixes, changing standards, equipment upgrades and addition of services, continues to grow rapidly in importance," said Stan Kopec, vice president of corporate marketing. "For the first time, Lattice's unique TFR capability, enabled by our LatticeXP silicon and ispVM programming tool, makes transparent field reconfiguration a reality without appreciable system downtime."

The TransFR flow

TFR simplifies the task of field logic reconfiguration in four steps. First, the LatticeXP device's on-chip flash memory is programmed while the device operates out of SRAM. Second, the I/O states are locked at their current or fixed value by issuing commands through the JTAG interface; device operation is then suspended.

Third, a command is issued through the JTAG interface to update the SRAM configuration from flash, which typically takes less than 1mS. And the final step is the on-chip logic resumes operation. It is functional and responding to inputs, allowing it to be placed into a known state. A command is then issues through the JTAG interface to release the I/O.

Steps two through four are executed with just one ispVM command. The latest version of the ispVM tool, 15.2, is available for download free of charge at the company's website.

- Ismini Scouras


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