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Experts mull interconnect beyond 65nm

Posted: 08 Jun 2005 ?? ?Print Version ?Bookmark and Share

Keywords:ic? interconnect? 45nm? interconnect technology conference?

A panel at the International Interconnect Technology Conference here examined the vexing question of the IC interconnect stack at 45nm and beyond.

The discussion was marked by a mix of confidence from the equipment industry, caution from foundries and skepticism from the chip design community.

University of Florida professor and panel chair Scott Thompson warned: "The industry has done a poor job of discussing where back-end of line (BEOL) technology is going," he said. "Today our first efforts at low-k materials are a success. But interconnect issues could still limit Moore's Law. And it's not just a matter of continuing to scale k to lower numbers. There are more issues involved."

AMD Corp. Fellow Paul Besser echoed Thompson's warning: "Interconnect has to be the perfect compromise. If you are too aggressive, you will miss the market window. If you are too conservative, you will miss the market requirements.

"The right answer will have to have a k in the neighborhood of 2.3 combined with a high modulus. Beyond just finding the right material, there will be many other steps that will have to be right." In particular, he said manufacturers "need to get better at cleaning out vias, at making repairs to the seed layer, and in dealing with the cap layer. Also, interactions between the chip and the package will be challenging."

John Chen, vice president of advanced technology engineering at fabless nVidia, added specifics from the chip designer's perspective. "Chips are not getting smaller," he observed. "That means that resistance is getting to be a real problem. In particular, as line widths get close to the electron mean free path, the increased resistivity slows down scaling. We have to find a solution, because there is no new material waiting out there beyond copper. In addition, we have to get to ultra-low k, now. But it must be a scratch-free material."

Chia-Hong Jan, senior BEOL program manager at Intel Corp., also addressed package interactions. "We look at what we call stress over strength," Jan said. "The strength of the materials in the interconnect stack has to support the stresses placed on the chip by the package. So that ratio, stress over strength, can't keep going up. We need both stronger interlayer dielectrics and lower-stress packaging technology to go forward."

Robert Wisnieff, senior integration manager at IBM, offered a pragmatic view. "Manufacturability and reliability will dominate our technology decisions," he said. "Those considerations dictate that we make the fewest changes possible while going forward."

Douglas Yu, senior director of advanced module technology at Taiwan Semiconductor Manufacturing Co. Ltd., sounded a conservative but positive note. "The combination of copper and low-k materials will continue to scale, all the way to perhaps the 22-nm node," he proclaimed. "We will have an intrinsic k of 3.0 ready for the 65nm node, 2.5 for the 45nm and 32nm nodes, and 2.0 in time for the 22nm and 16nm nodes.

"This won't be through radical change. It will be a step-by-step process, requiring close cooperation among materials and tool providers, assembly houses, foundries and our customers," Yu added.

Farhad Moghadam, Applied Materials Inc.'s thin films group senior vice president, listed steps required during the evolution. "One big issue is mechanical properties," he said. "All of the mechanical properties are important to the one critical parameter-crack formation velocity. Without introducing some new technology, lower-k materials are simply too fragile.

"But there are other vital changes as well," Moghadam continued. "As metal scales, the barrier/seed layer becomes a larger portion of the cross-section area. We can't give up that area any more. So we are developing techniques to directly electroplate copper onto the barrier."

Asked what the solution was to what Thompson called a catastrophe of increasing interconnect RC, the panel had a variety of responses. "Only about ten percent of designs are really RC sensitive. The rest are slow enough that you don't have to worry about it."

"Yes, but that's the ten percent you make money on," Besser countered.

Asked about chip reliability, Moghadam warned "the more interfaces you have, the more sites you have for reliability problems. If you want the chip reliable, keep the stack simple."

Intel's Jan added that the issue involved more than just the interconnect stack. "The biggest reliability problem I see is from the package stresses," he said. "In particular, the push to lead-free packaging materials is a disaster - lead-free materials substantially increase processing temperatures."

Wisnieff cited another concern. "With ultra-low-k materials, we know that moisture ingress leads to delamination - it's a serious problem. And stiffer off-die interconnect is just going to make the problem worse."

Asked about overall progress on k, the panel largely agreed with Jan's assessment: "We are only going to see about ten percent improvement in the effective value of k per node. That's reality," he stated.

Wisnieff countered that if the gain was only going to be ten percent, they would have to get much better at controlling variations. "Controlling variability will make the designer give back everything you've gained in effective k," he said.

Chen discussed how designers might cope. "Local routing is going to be OK," he stated. "For global routing, you are going to have to relax the dimension rules to manage RC. But then there's the problem of lots of I/O. If you have relaxed layout, high I/O density means lots of vias - and that means lots of delamination-related reliability issues."

- Ron Wilson

EE Times

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