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Cadence Virtuoso NeoCircuit completes Oki IP analog designs

Posted: 13 Jun 2005 ?? ?Print Version ?Bookmark and Share

Keywords:virtuoso neocircuit? oki electric? analog blocks?

Cadence Design Systems Inc. and Oki Electric Co. Ltd have disclosed that Oki achieved five times faster design turn-around-time for its analog blocks than with its previous design methodology and has completed 30 reusable analog IP designs using Cadence Virtuoso NeoCircuit technology.

Oki's designers were looking to reuse the analog IP they had already created without having to manually repeat design work. The use of the fully tested IP reduced the need for and time spent on expensive verification cycles and silicon re-spins.

Since adopting Cadence's NeoCircuit technology in December 2003, Oki has been using it to design analog circuits for personal mobile market-use LSIs, sound generator LSIs, memory LSIs including P2ROM, DRAM and FeRAM, FPD driver LSIs for TFT-LCD and OLED. With the technology, they have been able to achieve five times faster design turn-around-time than with their previous design methodology.

Analog circuitry is challenging to design, and analog content is extremely sensitive to process variations. These challenges can adversely impact chip yields. Cadence Virtuoso NeoCircuit technology speeds SoC and analog/mixed-signal design and improves quality by providing design exploration, design centering, and circuit and layout optimization early in the design cycle. This enables designers to optimize circuit specifications while taking into account manufacturing variations. The net result is higher-performance designs with improved yield in less time. Moreover, circuits created with this design methodology become analog IP that designers can reuse and retarget to new processes, speeding time to market.

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