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TSMC releases reference design flow for 65nm processes

Posted: 13 Jun 2005 ?? ?Print Version ?Bookmark and Share

Keywords:65nm manufacturing process? dfm tool? eda?

Taiwan Semiconductor Mfg Co. Ltd has released version 6.0 of its reference flow, the sequence of EDA tools that the world's largest foundry recommends for its 65nm manufacturing processes.

Separately, TSMC also announced design-for-manufacturing (DFM) tools and services intended to improve customers' yield and performance.

Ed Wan, TSMC's senior director of design service marketing, characterized the release of the new flow as an important step in TSMC "leading the industry to 65nm." Wan said TSMC worked with EDA vendors - chiefly Cadence Design Systems Inc. and Synopsys Inc. - to ensure that tools were available to support its 65nm process flow.

The highlights of the flow are new tools for dealing with power management and new DFM rules and features.

"Leakage is very important at 65nm," Wan said. "That's really the focus of reference flow 6.0."

TSMC unveiled its 65nm process at its Technology Symposium in April. The company expects to begin 65nm production in December. Wan said the company would uncharacteristically roll out the low-power version of the process before the high-speed and general purpose versions, in response to customer demand.

Version 6.0 adds new voltage scaling and power gating techniques to address heightened power management concerns.

"The flow is attacking the power management problem from two different directions," Wan said. "Its contribution to low-power design is pretty pervasive."

A key element of 6.0 is an integrated library and reference flow, including lower-power Nexsys libraries that were not available in version 5.0.

Individual Cadence, Synopsys tracks

Wan said TSMC works predominately with Cadence and Synopsys on the reference flow based on customer demand. TSMC also works with a handful of other EDA companies that provide individual tools for the flow, he said.

"We want to maintain a 'dual track' program that includes Synopsys and Cadence tools," Wan said. "We want customers to be able to utilize their existing tool investment within our flow. We don't want them to have to buy new tools."

As a result, 6.0 includes both a Cadence track and a Synopsys track. Each predominately uses tools from these major vendors, with tools from Mentor Graphics Corp., Arenta Inc., Apache Design Solutions and Optimal Corp. sprinkled in to fill holes in the flow.

Version 6.0 addresses DFM with new routing features and automation, including automated "dummy" metal fill and half-track wire spreading. Several of the recommendations that TSMC had issued for 90nm DFM have become design rules in the 65nm flow.

TSMC also announced the Yield Plus set of process-based tool kits and a set of design services known as Yield Pro.

Yield Plus contains DFM advisories, including rules, recommendations and guidelines for DFM. Among the guidelines is an optical proximity correction (OPC)-friendly guideline that TSMC said reduces OPC cycle time and file size and cuts photomask-making time by 10 percent.

Yield Pro is a collection of several services that are implemented by TSMC at the manufacturing stage, including a lithography process check, a yield sensitivity analysis, a package modeling service and scan diagnostic services.

TSMC's DFM solutions differ from other DFM tools in that they are based on TSMC's manufacturing data and expertise, Wan said.

"What DFM provides is a way to capitalize on a designer's best efforts," Wan said. "The designer is very competent and knows his job. What he doesn't know are a lot of the nuances of the process technology."

Yield Plus and Yield Pro are available to TSMC customers at an additional cost.

- Dylan McGrath

EE Times

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