Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

You can do better, survey tells EDA

Posted: 14 Jun 2005 ?? ?Print Version ?Bookmark and Share

Keywords:eda tool?

More than 1,000 EDA tool users are handing their vendors a report card at the Design Automation Conference here this week, and the grades can best be described as "incomplete."

In an exclusive electronic design automation survey conducted by EE Times and co-sponsored by Deutsche Bank, designers of ICs, field-programmable gate arrays and printed-circuit boards had some yeas and nays for their design aids. They like tool technology but want lower prices, more flexible licensing, better quality, interoperability and better software for emerging challenges such as power and signal integrity.

Respondents didn't hold back. "You aren't keeping up with the technology curve, yet EDA software costs are taking a larger and larger share of the total IC design budget at a rate second only to mask costs," said one IC designer.

"Clean up your act!" said a pc board designer. "Users are tired of abandonware, buggy products and designs that get locked into a particular EDA vendor's tool set."

"If you sell chips, then your EDA tools should be free," said an FPGA designer. "Don't make your software division a P&L center."

Survey results are based on detailed responses to a questionnaire filled out by 339 ASIC/IC designers, 116 FPGA designers and 698 board designers working in many application areas at large and small companies (see stories, pages 24 and 51). The results revealed some striking similarities among the three designer groups. For example, respondents in all three categories identified technology and ease of use as the two most positive aspects of their experiences with EDA vendors and cited licensing, interoperability and pricing as the three most negative. Most responses came from the trenches. Only about 20 percent of the three surveyed groups identified themselves as managers.

User satisfaction ratings for tool vendors were mixed, ranging from 30 to 80 percent. Deemed best of the lot were Novas Software Inc. (among IC designers), Synplicity Inc. (FPGA designers) and The Mathworks (board designers). Using a five-point scale where a "5" meant very satisfied and "1" meant not at all satisfied, respondents rated only vendors whose products they use or have purchased. The "5" and "4" choices were converted to a single percentage. So if all respondents gave a vendor a "5" or a "4," its user satisfaction rating would be 100 percent.

Those in all three of the designer groups said they are most satisfied with the accuracy of their EDA tools and least satisfied with automation, interopera-

bility, cost of purchase and cost of ownership. But "satisfaction" is a relative thing. Only 40 percent of IC designers said they are fully satisfied with accuracy, and most said that at least some work is needed in every major tool category.

EDA industry executives reached last week didn't appear surprised by some of the survey's key findings. Aart de Geus, chief executive officer at Synopsys Inc., agreed that pricing is a key concern for users. "The semiconductor industry is more driven by consumer products and is very sensitive in its overall cost equation," he said. "People are looking for ways to shave off costs, and tools are a factor."

Rajeev Madhavan, CEO at Magma Design Automation Inc., told of one IC customer who wanted to reduce the price of a consumer DVD chip from $45 to $30. His first thought? Trimming his EDA budget. "We have trained customers that [EDA vendors] are easy to be pushed down," Madhavan said.

De Geus conceded that interoperability is a problem. "In many ways the Frankenstein flow of gluing things together has become dramatically more painful," he said, adding that the problem is being addressed through integrated platforms.

Walden Rhines, CEO of Mentor Graphics Corp. and current chairman of the EDA Consortium, said that the survey methodology - based on polling of EE Times subscribers - would tend to skew it toward users of low-cost tools. "There has always been cost pressure, but EDA costs are insignificant compared to the cost of respins or lost engineering time," he said.

Reasons for unease

If designers appear uneasy, there is striking data in the survey showing why. In two years, 63 percent of ASIC/IC respondents expect to be designing chips at 90-nanometer or finer line widths, and 36 percent expect to be working with more than 10 million gates. Twenty-two percent said they're working at clock speeds of better than 1 GHz today.

FPGA designers, meanwhile, see a median expected gate count of 2 million in two years. They generally expressed higher levels of EDA tool satisfaction, and less concern about pricing, than their IC or pcb brethren.

For their part, pc board designers expect median board speeds of 241 MHz in two years, with 30 percent of nets falling into the high-speed category. This is a diverse lot who are also designing FPGAs, writing embedded software and running analog simulation. Their main concern is meeting cost budgets.

Topping the list of concerns for IC and FPGA designers are timing closure, power and completing functional verification. All three groups cited signal integrity as a major and a worsening problem, and all indicated a relatively low level of satisfaction with existing signal integrity tools.

On the board front, "Fix your bugs," said one designer. "Don't give me more features until the ones you currently have work properly."

While many EDA vendors are switching to time-based licenses, 37 percent of IC designers, 57 percent of FPGA designers and 62 percent of board designers prefer the old-fashioned perpetual licenses. Board designers in particular want licenses that are portable across platforms.

"License management is the most frustrating aspect of the EDA business," said one chip designer. "A perpetual license should be perpetual. I shouldn't have to worry about getting license renewals and dealing with what happens when a company goes out of business."

What about jobs disappearing to India or China? The survey, made up mainly of respondents from North America, suggests there's no massive exodus. Respondents said most chip and board design tasks are done in-house. Some work is outsourced to Asia, but the bulk of contract work goes to domestic companies.

"Right now, the more-advanced designs are done in North America, but I think that will change in the future," said Michael Fister, CEO of Cadence Design Systems Inc. "The industry is facing competitive pressures from increasingly talented design teams [abroad]."

- Richard Goering

EE Times

Article Comments - You can do better, survey tells EDA
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top