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Cadence details enterprise verification strategy

Posted: 15 Jun 2005 ?? ?Print Version ?Bookmark and Share

Keywords:verification process automation? vpa? dac? design automation conference?

Cadence Design Systems Inc. outlined the company's strategy for "enterprise" verification process automation (VPA) at a breakfast for journalists and analysts Monday (June 13) kicking off the Design Automation Conference (DAC).

Moshe Gavrielov, former Verisity Ltd CEO and now executive vice president of Cadence's new Verification division, said the industry needs to adopt a new methodology for dealing with the challenge of verification amidst the rise of device complexity.

"This is a huge, huge problem," Gavrielov said. "The complexity of some of these devices is mind boggling. The way to address it is not with another tool or language. It requires a whole new methodology."

Gavrielov said the EDA industry could use the model provided by enterprise business software and provide solutions tailored to the unique demands of various vertical markets. Gavrielov outlined a Cadence VPA strategy to link design and verification specialists and offer a blend of e, SystemVerilog and SystemC languages. This strategy, Gavrielov said, is similar to approaches established by leading enterprise software companies such as SAP and Oracle.

Enterprise VPA, Gavrielov said, would enable greater collaboration between engineers with differing skill sets, reducing the burden of verification.

To support this strategy, Cadence plans to develop a layered set of verification capabilities optimized for various market segments. Each layer will include process-automation capabilities that link and manage the activities of multiple design and verification specialists from plan to closure across block, chip and system levels, the company said.

Veteran EDA analyst Erach Desai pointed out to the audience that the strategy is similar to the enterprise verification strategy Gavrielov introduced two years ago while with Verisity. Cadence acquired Verisity in April.

Gavrielov characterized the Cadence VPA strategy as broader and more comprehensive than the Verisity strategy had been prior to the acquisition. "Under Cadence, the advantages of enterprise verification really shine," he said.

Cadence said its Incisive functional verification platform would be comprised of tightly integrated products and methodologies, including full integration of the vManager plan and metric-driven verification into the entire Incisive portfolio.

Gavrielov said that the complexity of devices is creating major problems for designers and tremendous opportunity for EDA.

As a testament to the increasing burden of verification, Keith Clarke, vice president of engineering at ARM, told the audience that about one-third of ARM's design team is now comprised of verification specialists and that the other designers spend half of their time on verification. By contrast, he said, 90 percent of the company's designers used to be register transfer level (RTL) designers with a few verification specialists.

Gavrielov said Cadence would continue to support various languages, including e, based on continuing customer demand.

"Don't believe what you are hearing that there will be one language to solve all of these problems," Gavrielov said. "That may happen at some point in the very distant future. The reality is that customers use a lot of different languages, and they all provide specific attributes."

- EE Times

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