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ASICs, ASSPs near extinction

Posted: 16 Jun 2005 ?? ?Print Version ?Bookmark and Share

Keywords:asic? assp? soc? risc? cpu?

The debate over FPGAs as a viable alternative to ASICs and ASSPs has been ongoing for nearly a decade. Industry analysts such as iSuppli and Gartner Dataquest have documented the decrease in ASIC design starts and the increase in FPGA design starts.

Next-generation platform FPGA devices based on 90nm have expanded high-performance processing and system integration options. They continue to push ASIC design starts lower as additional application solutions are defined.

With the beginning of the new millennium, the debate continued with the introduction of xilinx Virtex-II and Virtex-II Pro devices. These high-performance devices, with their flexible device integration capability, programmable I/O and lower overall design cost, helped usher in and establish SoC design methodology and quickly assumed many ASIC SoC designs.

The addition of high-performance RISC CPUs, block RAM, multigigabit high-speed serial I/Os, dedicated DSP functions and other system enhancements introduced technological advances that further solidified the rise of platform FPGAs over their ASIC counterparts. To get high-performance DSP processing or connectivity features for a specific applications domain, designers were typically forced to purchase the largest and most expensive devices. Larger parts had the biggest helpings of advanced features, while smaller parts had reduced portions of the same.

A new breed of domain-optimized, multiplatform FPGAs like Virtex-4 promises multidimensional application scaling based on required features and cost goals that are based on the advanced silicon modular block (asmbl) architecture.

Right mix

A specific platform can be optimized specifically for a certain domain of applicationse.g. logic, DSP, connectivity and embedded processingto meet application requirements previously delivered only by fixed technologies like ASICs and ASSPs while remaining programmable at heart.

Not only do designers have a choice in selecting the most suitable platform, but they can also choose the device size with just the right mix of capability and performance at the lowest possible cost.

The flexibility and ability to create optimal application domain subsystems set an even higher standard for FPGAs. Devices that are both hardware- and software-programmable enable more flexible implementation options than ASIC or ASSP devices. Reinvestigating, changing and enhancing system architecture at any time in the development process are possible. Designers can use this capability to evolve hardware in the field to meet new requirements or avoid expensive hardware upgrades.

FPGAs have demonstrated a clear and consistent trend in reducing cost and making FPGA technology more suitable for a wider range of applications. The combination of 90nm silicon fabrication technology with 300mm wafers results in a cumulative effectincreasing the number of die-per-wafer five times over previous devices. Increasing the die-per-wafer, together with architectural integration, enables substantially lower system costs.

A key component often overlooked in favor of programmable logic's economic advantage is shown in how technology is used throughout the world. No two people use the same technology, systems or software, nor do they want the same content.

Higher costs and longer design times for ASICs and ASSPs relegate their primary uses to proven lower-risk, very-high-volume applications. The rapid increase in ASIC development costs gives the advantage to platform FPGAs in today's advanced applications. The overall cost benefit of zero NRE pushes the high-volume ASIC or ASSP crossover point upward, locking in FPGAs like never before.

Domain-optimized multiplatform FPGAs accelerate the deployment of FPGA technology into many more application areas. The combined leverages of reduced risk, dramatically shorter design cycles and zero NRE will soon move all but the highest volume applications away from cell-based ASIC implementation toward more flexible architectures.

- Richard Sevcik

Executive Vice President

Xilinx Inc.

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