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FPGAs/PLDs??

Platform SoCs now possible

Posted: 16 Jun 2005 ?? ?Print Version ?Bookmark and Share

Keywords:soc? asic? portable media player? platform soc? rtl?

End markets are presenting a serious problem to traditional ASIC design. Especially in consumer applications, but increasingly in other areas as well, markets tend to be fast-moving and fragmented. The SoC that is perfect for midrange portable media players in China now is wrong today in the rest of the world and will be wrong tomorrow in China. SoC developers talk about product lives in months and hundreds of thousands of units, not years and millions.

Nothing could be a worse fit for the ASIC technology road map, which pushes foundries to 300mm wafers, yielding thousands of possibly useful dice apiece, and shoves design teams into longer, more-expensive design cycles. It quickly becomes infeasible for design team and foundry alike to make SoCs for such volatile markets. Yet in most of these markets, FPGAs are out of the ballpark in terms of cost and power consumption, and they may not meet performance goals either.

One strategy suggested for beating this problem is to embed a portion of configurable logic and memory into an SoC. In this way, a platform SoC can be designed that spans a wide range of markets. The configurable portion of the chip can then be used to fit the platform ASIC to a particular market.

Great idea, but to a large extent it has been science fiction until now. In recent months, Paris-based IP house M2000 announced that STMicroelectronics was using its embeddable FPGA fabric in chips. eASIC Corp. also made a similar announcement for its one-mask-configurable array and disclosed an instance in which an ST design team was able to go from RTL to tape-out in 24 hours on a new variant of an SoC. Lightspeed Semiconductor also unveiled a different approach to metal-mask configurability, promising performance and density close to cell-based schemes, but with no need to port physical IP to the user's process.

The eASIC announcement is not for a new product, but merely for fulfillment of a claim made consistently over a number of years by the company. ST, according to the two companies, has designed an eASIC fabric into a 150nm, six-metal platform SoC along with an ARM 946 CPU, an AMBA bus architecture and some general-purpose peripherals. The concept was that ST designers would write RTL for application accelerators and protocol engines to fit the platform device to a particular application.

"We have so far created six derivative products from this design," said Michele Borgatti, front-end technology and manufacturing manager on the overall project at STMicroelectronics. "In one instance, we were able to move from completed RTL to tape-out of the necessary via mask in 24 hours."

If the company combined this capability with the ability to substitute e-beam-on-wafer writing for the via layera capability ST has already demonstrated "we could reduce the fab turnaround to a few weeks," Borgatti said. "This means that in a few weeks, we could go from completed RTL to sample silicon on a new derivative of a platform SoC."

This is of enormous strategic importance to ST, he said. It allows the company, once a platform chip has been defined and the front-end processing completed on a bank of wafers, to retarget the platform instantly to a small, fast-moving market. "This way, we can justify the ASIC design on the return from a number of derivative products, rather than try to recapture the full cost of design from a single opportunity," Borgatti said.

An important part of the effort was to define macros at the physical interface between the platform logic and the eASIC fabric that permitted the two to be analyzed separately for signal integrity. This allows ST to use eASIC's closure tools without reanalyzing the entire SoC design for timing, signal integrity and power droop. Otherwise, a substantial portion of the back-end ASIC design would have to be repeated for each derivative.

Overhead

But the flexibility exacts costs in performance and density, Borgatti said. "There's about a 25 to 30 percent area penalty and about a 1.5x difference in maximum speed between the eASIC fabric and a fully cell-based implementation of the same RTL," he said. "But since we don't envision an application where the eASIC fabric would be more than about 30 percent of the die area, this is not a significant issue compared with the turnaround time."

ST also plans to exploit the fact that underlying eASIC logic elements are SRAM-based lookup tables (LUTs) rather than hardwired gates.

"We see this as valuable in three areas," Borgatti said. "First, it allows us to make simple functional changeslike complementing a signal to fix a common design errorby simply changing the bit stream loaded into the LUTs. Second, it allows us to isolate the component nets that flow into an incorrect signal during debug to isolate the source of the error. And third, it allows us to greatly accelerate test time by reconfiguring the LUTs to implement XOR functions, making everything much better for automatic test pattern generation."

Borgatti sees the eASIC fabric as complementary to the M2000 FPGA fabric ST has also licensed and used. "The eASIC fabric can accommodate about 300Kgates, but it requires somewhat larger volumes to justify it," he said. "The M2000 FPGA-based fabric has a smaller capacity, at a few tens of thousands of gates, but it is bit-stream-programmed, so a part can be created for a very small potential market."

Embeddable fabric

Both the M2000 and eASIC approaches are offered to the licensee as physical IP that must be ported to the particular process variant the user intends to employ. Lightspeed Semiconductor, late of the structured-ASIC business, is now offering an alternative: an embeddable, metal-configured logic and memory fabric that is implemented from the user's standard cells. No custom cells or structures are involved, unless the user wants to employ Lightspeed's custom-configurable I/O cells. So the Lightspeed IP can be used directly in whatever process the customer is now running, without bringing in any new physical design at all.

"We select a dozen or so of the simple cells from the customer's synthesis library," said Dave Holt, president and CEO at Lightspeed. "Then we build our fabric up out of what we call macroblocks. Each block is identical, about 37m on a side in 130nm, and each is constructed entirely out of the standard cells.

"Each block is capable of implementing literally hundreds of logic functions, simply by changing the upper interconnect metal and via layers."

Those hundreds of functions are then put into a library and used by the customer for synthesis. The result of the synthesis is a netlist of Lightspeed cells, which are then mapped by a proprietary tool onto the macroblocks. The same mapping tool also does clock and buffer insertion and preliminary timing analysis. Scan cells are included in the macroblocks, so the synthesized design is scan-ready.

The result, according to Holt, is a logic and memory fabric that can be configured to implement any reasonable RTL. Depending on the performance and density the customer needs, anywhere from two to all metal and via layers are needed to configure the fabric.

- Ron Wilson

EE Times




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