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Less is more with FPGAs

Posted: 16 Jun 2005 ?? ?Print Version ?Bookmark and Share

Keywords:fpga? asic? pld? soc? die size?


When FPGAs first arrived in the market, they were hailed as a low-cost alternative to ASICs. Free from mask charges and allowing painless design alterations, all FPGAs seemed to need was just a little more capacity to be able to replace ASICs in all but high-volume production. However, experience has shown that for FPGAs to become production-quantity alternatives to custom logic, it is more appealing to have less logic capacity.

One of the reasons for this trend is the die cost of programmable logic. In a given process, programmable logic typically needs 50 to 100x the die area of dedicated logic to achieve the same functionality. Component cost is directly related to die area, so FPGAs end up being more costly than dedicated logic counterparts.

This enlarged die footprint is not a problem for smaller FPGAs. Such devices are typically pad-limitedi.e. die size is set by the I/O pin count, not the gate count. As long as enough logic capacity fits within the available space, area cost is irrelevant.

Since a smaller size eliminates the FPGA's cost penalty, such devices have found their way into volume production. A big market is the replacement of PLDs for the design of glue logic and other small custom logic elements. One reason for this is that FPGAs make memory elements, while other PLDs typically do not have a memory. Many modern systems use serial I/O structures that need some buffer memory, even in the glue logic.

Complex SoC designs are not pad-limited, so the die area penalty of programmable logic hits full force. The traditional response in programmable logic has been to shrink the process to reduce the area needed for a given functionality. While that lowers the FPGA's cost, it raises a new concernpower.

A million-gate-equivalent FPGA consumes a significant amount of power just to hold its configuration. Furthermore, because the circuit uses more transistors to implement a given logic block, it uses more operating power than an equivalent ASIC. Shrinking the process compounds power concerns. Smaller process geometries have increasing levels of leakage current, so the standby and idle currents of large FPGAs start becoming excessive. Trying to make a large FPGA less expensive to purchase can thus make it too power-hungry for many applications.

The initial advantages seen in FPGAs, such as design flexibility, no mask charges and no minimum order quantities, are still valuable assets. If anything, they have increased in value as mask costs push toward $1 million a set and the penalty of design errors increases in proportion. The more-is-better approach to FPGAs, however, is not leveraging these assets effectively. Smaller amounts of programmable logic, mixed with fixed conventional logic, can be more efficient in terms of die size and power consumption.

Consider a million-gate equivalent FPGA. If you replace 10 percent of the programmable logic with fixed logic, such as a processor core, you can get the equivalent of nearly 6Mgates in the same die size, assuming a conservative 50:1 FPGA die area penalty. Increase that substitution to 50 percent and you get a 25Mgate equivalent, which is more than enough for most SoC design needs. Reducing the amount of programmable logic can vastly increase functionality within a given die size.

Such hybrid device designs provide other options as well. For the same functionality as the million-gate FPGA, a hybrid design would occupy less die area, thus costing less. The hybrid design could also be implemented in a more mature and mainstream process technology. The die area would not be as small, but the leakage currents would decrease, making it a lower-power alternative.

Mixing fixed and programmable logic makes sense, especially for large designs. While glue logic and other small design elements are almost all custom logic, most large designs use many standard elements such as RISC processors, Ethernet MACs and parallel I/Os. Designers gain no advantage in creating such elements in programmable logic, so they are perfect candidates for fixed-logic implementation.

To some degree in general applications, and an even greater degree in vertical markets, mixed programmable and fixed-logic devices can find a home. These hybrid devices, sometimes called platform FPGAs, have already begun appearing in the market. They offer a combination of the FPGA's flexibility with the cost-efficiency of fixed logic. The key is finding the right mixture.

Many first-generation offerings were somewhat tentative in their use of fixed logic, incorporating only a processor core or a few other functions. While a step in the right direction, they provided limited benefit. The advent of more balanced mixtures is now turning the platform FPGA into a compelling alternative to either ASIC, structured ASIC or pure-FPGA design approaches for medium-production volume designs.

Finding the right balance is the challenge. Too much programmable logic increases the cost and power penalty; too much fixed logic narrows the range of a platform FPGA's applicability. Without a broad application base, the platform FPGA does not achieve the market volume needed to minimize unit cost.

Depending on the market, it appears that ratios of 50:50 or higher are required to strike the right balance between capability and affordability.

Whatever the right mix may prove to be, it is clear that large FPGAs will never become a high-volume solution to system design problems. Small custom designs or large designs that are one part programmable and one part fixed will become the mainstay of programmable logic. In either case, less is more for FPGAs.

Tim Saxe, VP of Engineering

Brian Faith, Director of Logic Products

QuickLogic Corp.

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