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TI outlines further CMOS scaling

Posted: 17 Jun 2005 ?? ?Print Version ?Bookmark and Share

Keywords:vlsi technology? ully-silicided? nickel silicide? semiconductor?

Texas Instruments Inc. (TI) is presenting papers that describe key accomplishments on advanced materials and manufacturing process development at the 2005 Symposium on VLSI Technology. The company's contribution highlights a comprehensive R&D strategy designed to combine in-house initiatives with close collaboration among industry consortia and universities to deliver the semiconductor innovations critical to TI's customers.

At the VLSI Symposium, TI and key development partners are presenting a number of key findings, including a demonstration for the first time the scalability of fully-silicided, nickel silicide (NiSi) gates to 30nm and below. The approach promises to ease the transition from current polysilicon gate electrodes to full-silicidation-of-polysilicon (FuSi), resulting in cost effective integration of metal gates. Leveraging current materials and providing the least amount of changes to today's process flow delivers a highly efficient, easy-to-integrate method to enhance performance.

TI also participates in research efforts that focus on the advancement of non-planar triple-gate devices, and is discussing fabrication of the industry's smallest 6T-SRAM cell with multi-gate devices at the VLSI Symposium. The accomplishment is based upon work done within the IMEC European nanoelectronics research center as part of a sub-45nm CMOS program. TI utilizes 6T SRAM cells as the primary embedded memory in its CMOS products today. Migrating to tri-gate non-planar transistors may extend the use of 6T SRAM cells to the 32nm node or beyond. The approach maintains design compatibility with conventional SRAM approaches and significantly shrinks previously designed triple-gate SRAM device cells, further improving performance and integration options.

TI is also presenting research through work with SEMATECH on the compatibility of non-planar multi-gate transistor approaches with conventional CMOS approaches by introducing strain to improve the drive current of future transistors by as much as 25 percent.

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