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Grace adopts Synopsys tool suite for chip production

Posted: 20 Jun 2005 ?? ?Print Version ?Bookmark and Share

Keywords:grace semiconductor? optical proximity correction? design for manufacturing?

Mainland China-based pure IC foundry Grace Semiconductor Mfg Corp. has adopted U.S.-based Synopsys Inc.' design for manufacturing (DFM) tool suite, particularly using the Proteus optical proximity correction (OPC) software and SiVL lithography verification tool to lower mask turnaround time and to enhance its ability to produce high-yielding chips.

"Grace's standardization on Synopsys' DFM tool suite reinforces Synopsys' leadership in the design for manufacturing space," says Edmund Cheng, vice president of Marketing for the Silicon Engineering Group at Synopsys.

"We selected Synopsys' leading-edge DFM tool suite because it provides us with the most scalable and flexible solution available to improve the manufacturing process for both Grace and our customers," says Hao Fan, senior director of TD for Grace.

The distributed processing capabilities of Synopsys' tool suite enable Grace to deliver fast turnaround time in performing OPC, lithography verification and MDP. Synopsys' Proteus software and SiVL lithography verification tool reduce turnaround time by their ability to utilize hundreds of CPUs simultaneously.

"By using Synopsys' distributed processing architecture, we obtained near-linear scalability for OPC conversion. This substantially decreased our turnaround time without sacrificing the accuracy of our designs in silicon," adds Hao.

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