Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Memory/Storage

Sony, Toshiba co-develop 45nm embedded DRAM

Posted: 20 Jun 2005 ?? ?Print Version ?Bookmark and Share

Keywords:embedded dram? 45nm? sony?

Sony Corp. and Toshiba Corp. have reported they developed the first 45nm embedded DRAM cell by scaling embedded DRAM cells down to 0.069 square microns.

The companies' findings were reported in a paper at the 2005 VLSI Symposia held in Kyoto, Japan.

Sony and Toshiba jointly developed 90nm and 65nm process technologies, which Toshiba calls COMS4 and CMOS5 respectively. They are now in the third phase of the collaboration to develop 45nm process technology. Toshiba named the technology CMOS6, though Sony does not use this name.

For high performance system-on-chip LSIs, the team developed deep trench based embedded DRAM technology as the important on-chip memory.

When the embedded DRAM scales down, the capacitance of the deep trench capacitor decreases. To compensate for the decreased capacitance, the R&D team introduced a bottle etching process combined with a structure named LOCOS collar, which allows forming the trench in a bottle like shape. The trench, therefore, is wide but has a narrow month that increases the trench's surface area, increasing capacitance.

In addition to the bottle-like shape for the trench, high-K node dielectric material (Al2O3) is used in place of conventional nitride-oxide insulation.

"If these technologies are applied to CMOS5 (65nm generation), the capacitance is improved by 60 percent. That is, if the capacitance is to be the same level as CMOS5, we can make the trench smaller for CMOS6," said Tomoya Sanuki, a researcher at the System LSI division of Toshiba Semiconductor.

The data retention characteristics of the prototype 45nm DRAM are almost the same as that of the 65nm embedded DRAM, the team reported.

A hybrid STI (shallow trench isolation) structure and a new strap structure, also part of the embedded DRAM, improves performance and establishes the full process compatibility with the logic process.

A combination of spin on dielectric (SOD) and conventional high density plasma (HDP) films is used for high aspect ratio STI. As the SOD film has tensile stress and the HDP film has shrink stress, optimum control of the thickness of SOD film reduces the mechanical stress from STI.

"With introduction of the SOD film, the DRAM performance is improved by about 10 percent," said Kazunori Ohta, integration technology department of Sony's Semiconductor Technology development Group.

The joint team introduced a new structure named Ultra Shallow Buried Strap (USBS) in place of the conventional Buried Strap structure to shrink the distance between storage node and array transistor. While the Buried Strap requires an additional process to form a Ni silicide block in the strap, USBS eliminates the block but uses a Ni silicide layer in the strap.

"The use of Ni silicide causes leakage, but we devised a process to suppress it," said Ota.

As USBS eliminates the additional process, the embedded DRAM cell needs no extra processes after the formation of the deep trench. This means that exactly the same process flow is applied to logic transistors and array transistors.

Functional tests of the 256 kbit embedded DRAM macro cell produced a yield rate of 61 percent, reported the team.

Both companies invested about 20 billion yen for the 45 nm node process development. About 150 engineers of both companies in Toshiba's R&D center and Oita fab are establishing the key technologies for the 45nm generation by the end of fiscal 2006 (March 2007).

- Yoshiko Hara

EE Times

Article Comments - Sony, Toshiba co-develop 45nm embedd...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top