Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Renesas tapes out 90nm production using Synopsys Galaxy

Posted: 29 Jun 2005 ?? ?Print Version ?Bookmark and Share

Keywords:wireless? 90nm soc? design? galaxy design?

Renesas Technology Corp. has taped out a 90nm SoC design for wireless applications using Synopsys Inc.'s Galaxy design platform.

"With this being our 90nm wireless design, we were concerned about DFM issues," said Teruaki Harada, department manager of DFM & EDA technology development dept., design technology division, Renesas. "The yield enhancement techniques in Synopsys' Galaxy Design Platform, particularly the Astro product's ability to insert redundant vias and efficiently enforce antenna rules, helped us optimize our design and achieve our 90nm yield targets," Harada added.

The Renesas multimillion gate design was created using Synopsys' physical design solution -- the Design Compiler product for synthesis, the Power Compiler product for dynamic and leakage power optimization, the Physical Compiler and Astro products for physical implementation, and the Star-RCXT product for full-chip parasitic extraction.

The yield-aware routing optimization techniques in the Astro product -- such as redundant via insertion -- helped Renesas y minimize impact on timing-critical nets and optimize for yield while maintaining a predictable convergence to timing closure.





Article Comments - Renesas tapes out 90nm production us...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top