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DFM litho tool aims for two worlds

Posted: 01 Jul 2005 ?? ?Print Version ?Bookmark and Share

Keywords:lithography simulation? solid-e? design for manufacturing? dfm? full-chip image verification?

Moving to bridge the gap between design and manufacturing, Germany's Sigma-C has begun marketing its established Solid lithography simulation technology to designers.

The company introduces its new Solid+ product, which acts as a virtual exposure tool to simulate microlithography and identify potential problem areas during the design process. Solid+ can specify, among other things, whether patterns can be accurately produced by photoresist at smaller process nodes.

The technology is not new. For several years, Sigma-C has marketed a software package for simulating and modeling optical lithography. This product, known as Solid E (and its predecessor, Solid C) have found a market among process engineers looking to optimize lithography processes. Sigma-C claims to be No. 1 in lithography simulation licenses since 2003, with a customer base composed of leading semiconductor and IC manufacturing equipment companies.

What's new about Solid+ is that it is a design-for-manufacturing (DFM) product targeted at process engineers, designers and optical proximity correction engineers. Moving lithography simulation upstream in the process, Sigma-C claims, can reduce mask and engineering costs while improving chip yield and manufacturing time.

With a central database that provides design and process engineers with a common language for talking about DFM, Solid can become the lithography simulation equivalent of SPICE modeling, said Peter Feist, Sigma-C's chief operating officer.

"The design and lithography worlds never really had a common language to talk with each other until now," Feist said.

While other DFM solutions focus on full-chip image verification, trading simulation speed and area size at the expense of accuracy, Feist said, Solid+'s 3D technology simulates the aerial image to the macro level and the resist image to the cell level with no loss in accuracy. Solid+ also simulates cells of up to 100-by-100?m, Feist said.

Sigma-C was founded in 1987 by Christian Kalus, a former assistant professor of crystallography at the University of Munich in Germany. The company had been self-funded from its inception. But in 2003, seeing applications for his technology in the emerging area of DFM, Kalus secured roughly $3.2 million in venture funding.

Kalus used some of the capital to attract the talent that could move Sigma-C's technology into the DFM space, including Feist, a 20-year veteran of semiconductor industry executive management, and EDA industry veteran Thomas Blaesi, who is general manager of Sigma-C's U.S. subsidiary. Blaesi has worked at Cadence Design Systems Inc. and Synopsys Inc.

The result is a balance of semiconductor, equipment, design and EDA management experience that is unusual in the industry and, Sigma-C believes, will help the company's technology impact DFM on both sides of the fence.

Feist said Solid+ has been in beta testing with three major memory manufacturers over the past year. Memory companies, he said, have shown more immediate interest in Solid+'s benefits than their logic counterparts.

According to Feist, initial customer reaction has been positive. "Our customers are telling the EDA companies to calibrate their tools according to Solid," Feist said. "It's no exaggeration to say that Solid could become the lithography simulation equivalent to SPICE."

- Dylan McGrath

EE Times

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