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Cores ace networking benchmarks

Posted: 01 Jul 2005 ?? ?Print Version ?Bookmark and Share

Keywords:embedded microprocessor benchmark consortium? eembc? network processors? powerpc? tcp/ip layer?

Tensilica Inc. has scored a top ranking in the Embedded Microprocessor Benchmark Consortium (EEMBC) suites for network processors, beating the PowerPC and other architectures in tests that measure performance at TCP/IP layers. The benchmarks compared a special, optimized version of the Xtensa LX architecture with a standard version of Xtensa.

Steve Roddy, VP of marketing at Tensilica, said that prior to working with the EEMBC V2 network benchmarks, the company had never aimed specifically at packet-forwarding operations. But many networking customers have developed multicore versions of the LX, he said. Cisco Systems Inc. implements one of the most parallel versions, using 188 Xtensa cores for the Silicon Packet Processor in its CRS-1 core backbone router.

A critical aspect of network processors is not just the parallelism and deep pipelining possible with the architecture, Roddy said, but the ability to define deep ingress and egress queues for quality-of-service (QoS) prioritization. While this capability was not designed strictly with networking in mind, Roddy said, it fits the model of next-generation IP services well.

EEMBC's IPmark checks the validity of the IP packet header, the speed of network address translation operations and reassembly speed for pulling fragmented datagrams into one IP packet. On L4, the TCPmark measures TCP performance itself, the performance of open-shortest-path-first routing, the performance of QoS determination and overall route look-up speeds.

Test scores for IPmark, normalized by MHz, were 0.82138 for the optimized version of LX and 0.1751 for out-of-the-box LX. By comparison, a PowerPC 760GX scored 0.2861 and a PowerPC MCP7447A, 0.1751.

The test scores for TCPmark were 1.62434 for optimized LX, 0.33762 for standard LX, 0.4671 for PowerPC 760GX and 0.5856 for PowerPC MCP7447A.

"Even the standard LX did very well in the tests," Roddy said. "But when you can optimize queues and data flow, it really shows up in the higher-layer routing benchmarks."

Tensilica decided to use a 128bit interface for the processor to minimize load/store operations. Its designers used a flexible-length instruction extension (FLIX) methodology, similar to VLIW instructions, allowing parallel execution while keeping the code compact. A key element in optimizing Xtensa for packet handling was to expand on the core FLIX instruction set with Tensilica Instruction Extensions, or TIE operations, which are generated in a C/C++ compiler and look like C function calls. TIE states also are used internally to cache data during packet operations.

A dedicated TIE queue for packet headers was developed for the optimized LX.

For better packet control, designers can define finely grained input and output ports using TIE directly.

The EEMBC tests assume an LX configuration of 1.2mm? using a 130nm process and a standard-cell implementation. The core would consume 115mW at 304MHz. Code density of the LX is 65,208bytes, vs. several hundred thousand bytes in typical RISC-based packet processors.

- Loring Wirbel

EE Times





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