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Analog EDA firm tackles PLL noise

Posted: 01 Jul 2005 ?? ?Print Version ?Bookmark and Share

Keywords:silicon-proven eda? phase-locked loop? pll? noise analysis tool? tapeout?

Turning academic breakthroughs into silicon-proven EDA products is no small task, but the founders of startup Berkeley Design Automation Inc. claim to have done just that with a noise analysis tool for circuits that contain phase-locked loops (PLLs).

Berkeley Design Automation rolls out the PLL Noise Analyzer, a tool that uses the company's stochastic, nonlinear circuit analysis technology to analyze noise and jitter for PLLs. The technology was developed by founder and CTO Amit Mehrotra as part of his doctoral research at the University of California at Berkeley.

The technology has been proven on more than 35 customer designs and can shrink time-to-volume for both discrete analog/RF ICs and SoCs containing analog blocks, said Ravi Subramanian, Berkeley Design Automation president and CEO.

"Analog noise is the No. 2 reason for silicon respins," Subramanian said. "Analog noise is dominated by PLL phase noise and jitter. These circuits are pervasive, so they provide a good business opportunity."

Subramanian came to Berkeley Design Automation in August 2003 from Infineon, where he was VP and general manager of the W-CDMA business unit. Before that, he was CEO of Morphics Technology Inc., a fabless wireless semiconductor company that was acquired by Infineon.

After getting his Ph.D. from UC Berkeley in 1999, Mehrotra became a professor at the University of Illinois, where he continued his research. He teamed up with fellow Berkeley Ph.D. Amit Narayan, who had founded formal-verification provider Averant Inc. and went on to develop the Dolphin product for Monterey Design Systems. The two developed a business plan and secured $11 million in venture capital funding in March 2003.

"While I was at Infineon, I was put in touch with this team as it was jelling," Subramanian said. The introduction came through Rob Chandra, general partner at Bessemer Venture Partners and a member of Berkeley Design Automation's board.

Now, two years later, the company has a shipping product, tape-outs and a customer list that includes NEC, Fujitsu, Analog Bits Inc. and PA Semi Inc.

The new company is coming into a tough business. Automation has been a hard sell for analog designers, and a number of analog EDA companies have either gone out of business or been acquired by larger companies.

Berkeley Design Automation is different, Subramanian said, because the company is focusing on verification rather than design. "We believe that the key innovations that are really missing in advancing the state of analog EDA are in verification," he said.

Furthermore, he said, the company's value proposition is "unique" and the tool is easy to use.

PLLs ubiquitous

The new company does appear to be addressing a pervasive need. PLLs are widely used as golden timing and frequency sources; indeed, they are integrated into virtually every IC. The presence of PLL phase noise and jitter is also a primary cause of analog noise. It affects the receiver SNR, degrading signal quality, and can also affect the maximum frequency for processors and I/Os, Subramanian observed.

Today, designers rely on ad hoc techniques to predict PLL noise and jitter, Subramanian said. They may attempt to get a first-pass approximation based on linear models, but the models don't reflect how circuit noise becomes nonlinear as it travels through the circuit.

If designers use a SPICE simulator, the process may take weeksand it assumes a linear analysis, Subramanian said. What designers often end up doing, he said, is building a silicon prototype so they can accurately characterize phase noise and jitter.

Berkeley Design Automation's solution is a stochastic nonlinear engine. Based on Mehrotra's research at UC Berkeley and the University of Illinois, the approach includes algorithms that solve the stochastic, nonlinear partial differential equations that model the nonlinear, time-varying behavior of transistor-level circuits.

"Traditional 1G and 2G tools were solving voltage and current equations," Subramanian said. "The innovation here is introducing noise sources, as well as the nonlinear, time-varying way these noise sources transform through the circuit."

PLL noise analysis is just a start. "We'll certainly expand to other areas," Subramanian said. "There are a number of problems not analyzed by tools today because of the nonlinear and stochastic nature of many circuits."

The PLL Noise Analyzer takes in HSpice or Spectre netlists, along with standard BSIM models. It automatically runs the noise and jitter analysis. It reports jitter, phase noise across a frequency range and lists top contributors to the noise by device. Designers can then modify the netlist and run the analysis again until they converge on a design that meets specifications.

Subramanian said that a circuit with 1,000 to 5,000 devices can run in 45mins in a 2GB machine, compared with "days or weeks" for existing methods. Absolute results are within 2dB or 3dB of silicon, he said.

While Berkeley Design Automation is targeting analog designers today, a time may come for the company to cast a broader net.

"Many high-speed digital designers are very quickly becoming analog circuit designers," Subramanian said.

- Richard Goering

EE Times

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