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FPGAs offers better design margin

Posted: 04 Jul 2005 ?? ?Print Version ?Bookmark and Share

Keywords:xilinx? virtex-4? fx60? fpga?

Xilinx Inc. announced initial customer shipments of its Virtex-4 FX60 90nm FPGAs with integrated 622Mbps to 10.3125Gbps serial transceivers, promising to deliver better design margin and flexibility over any other competing high-speed serial I/O solution in the industry.

According to the company, they developed the Virtex-4 RocketIO transceivers to deliver ample high-end performance as well as the most design margin. For designs running at speeds lower than 10.3125Gbps, the designer is assured of higher bandwidth if required, said the press release.

The Virtex-4 FX60 devices support all major serial standards, including PCI Express, Serial RapidIO, Ethernet and Fiber Channel. These transceivers provide advanced equalization features such as 3-tap Transmit Pre-emphasis, Linear Receive Equalization, 6-tap Decision Feedback Equalization (DFE), and Integrated AC-coupling capacitor.

The Virtex-4 FX20 and FX60 devices are already available for orders today. Pricing for the Virtex-4 FX20 device with eight serial transceivers starts at $49.99 for 25,000-unit volumes in December 2005.

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