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Reference design offers TCP/IP connectivity on FPGA platform

Posted: 06 Jul 2005 ?? ?Print Version ?Bookmark and Share

Keywords:altera? interniche? morethanip? networking reference design? reference design?

Altera Corp. has teamed up with InterNiche and MorethanIP to provide embedded designers with a networking reference design for its nios ii embedded processor.

The networking reference design delivers more than 60Mbits of throughput via TCP/IP over a 100Mbit link. Embedded designers can use Altera's SOPC Builder tool and Nios II integrated development environment (IDE) to customize their reference design using MorethanIP's MAC-NET core and InterNiche's NicheStack IPv4 software stack.

"The versatility and performance of our NicheStack IPv4 protocol suite addresses the challenges faced by embedded systems development teams," said Larry Larder, president of InterNiche. "By enabling low-cost TCP/IP connectivity on FPGA designs with exceptional performance, we help to open up a new world of flexibility for the system designer," Larder added.

SOPC Builder enables the system engineer to add, edit and specify the connections between the Nios II processor, MAC-NET core and other peripherals in the system. It then connects all of the peripherals together using the high-performance Avalon switch fabric, enabling the MAC-NET core to efficiently move data through local memory resources.

"Embedded designers can use our Ethernet MAC with integrated hardware network protocol acceleration (MAC-NET core) to increase the networking performance for their embedded systems that require high throughput," stated Daniel Koehler, CTO at MorethanIP.

The reference design, the Nios II embedded processor and the complete evaluation toolset can be downloaded from Altera's website.

- Ismini Scouras


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