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Epson doubles productivity using Cadence RTL compiler

Posted: 15 Jul 2005 ?? ?Print Version ?Bookmark and Share

Keywords:encounter rtl? compiler synthesis? lcd controller?

Japan-based electronics device provider Seiko Epson Corp. (Epson) disclosed that it has doubled in the production tapeout of high-volume LCD controller chip using Cadence Design Systems Inc. Encounter RTL compiler synthesis.

Epson said it has achieved a 50 percent reduction in synthesis runtime, top-down synthesis and a clean netlist with the ability to route with no detours all contributed to timing closure and a substantial improvement in time-to-market.

The Encounter RTL compiler, part of the Encounter digital IC design platform, is claimed to shorten design turnaround time by delivering superior quality of silicon (QoS) through physical design. In addition to fast runtimes, Encounter RTL compiler offers a true top-down synthesis methodology to avoid the lengthy manual effort of block-level integration.

"LCD controllers are one of the most important products for Epson's semiconductor business, and design turnaround time is the most critical factor in maintaining our position in highly competitive market," stated Kanji Aoki, manager of the IC design technology department at Epson.

"With its leading-edge technology, Encounter RTL compiler helped us meet the design schedule. Our designers will continue to follow the top-down synthesis method enabled by Encounter RTL Compiler to maximize our time-to-market advantages," added Aoki.

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