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Actel rolls out new Libero IDE version

Posted: 15 Jul 2005 ?? ?Print Version ?Bookmark and Share

Keywords:actel? libero? integrated design environment? ide? fpga?

Actel Corp. introduced its Libero v6.2 Integrated Design Environment (IDE) that promises to enable FPGA designers to achieve the highest results in terms of quality, efficiency and functionality.

"This new version of our Libero IDE includes significant new functionality for design analysis and timing closure,&quot said Saloni Howard-Sarin, director of antifuse and tools marketing at Actel. "Users are able to apply constraints to their designs, manage and analyze the effects of those constraints, and drive their designs efficiently to timing closure, while achieving higher performance."

With Libero 6.2, Actel unveils its new smarttime static timing analysis environment, enabling customers to analyze and manage timing constraints, perform advanced timing verification, and ensure predictable timing closure through a tight integration with timing-driven place-and-route. In this edition of Libero, Actel and Mentor Graphics Corp. extended their partnership to provide Mentor Graphics' ModelSim AE simulation as an integral part of the Libero "Gold" package, which is now available to all Actel customers free of charge. Additionally, the Libero 6.2 IDE includes enhanced synthesis capabilities from Synplicity and physical synthesis features from Magma Design Automation. The IDE now runs on Linux and Solaris platforms.

SmartTime static timing analysis engine

SmartTime is a new powerful multi-view product developed by Actel to help designers perform detailed timing analysis and quickly determine the steps necessary to achieve design closure. The SmartTime Constraints Editor view enables users to list, edit and create precise timing constraints. It includes a graphical user interface with visual dialogs that guide users toward capturing their timing requirements and timing exceptions correctly. Another view, the SmartTime Analyzer, allows designers to perform per-clock-domain minimum and maximum timing analysis, and provides inter-clock domain analysis capabilities. The tool simplifies the analysis process by enabling designers to track paths with timing violations quickly. Designers can then directly set specific timing exceptions on the violating paths to tighten or relax the requirements and quickly iterate toward timing closure.

The Libero 6.2 IDE is available in a Platinum edition on Windows and Unix platforms, which sell for $2,495 and $4,995, respectively. It is also available on Windows in the Gold edition.

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