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Chip interconnect draws designers, too

Posted: 18 Jul 2005 ?? ?Print Version ?Bookmark and Share

Keywords:interconnect stack? uniprocessor chip? multicore chip? metal-3? patterning?

The eighth annual International Interconnect Technology Conference (IITC) opens to a growing!and unfamiliar!level of attention. Traditionally a highly specialized forum for process engineers who create interconnect stacks on ICs, the event has already begun to reach beyond its normal audience, attracting chip designers as well.

"Interconnect scaling is not like transistor scaling," said Mark Bohr, senior Intel Fellow. "As you make transistors smaller, they get faster. That is no longer true of interconnect. As you reduce the width of interconnect segments, you also have to reduce the thickness, and so the resistivity doesn't go down."

This fact was a significant factor in Intel Corp.'s shift from ever-faster uniprocessor chips to multicore chips, Bohr said.

John Martin, VP of strategic alliances and partners at Chartered Semiconductor Manufacturing Ltd, looked at the issues his organization sees in the transition from 90nm to 65nm interconnect and divided them into three categories: patterning, dimensional control and chip-to-package interactions. Of those, perhaps the most significant is patterning.

To deliver the density promised by those smaller transistors, the first few metal layers in a 65nm process must allow for very fine metal pitches. At 90nm, for the first time, the pitch on Metal-1 became so tight that optical proximity correction (OPC) was necessary to correctly render the patterns on the Metal-1 masks.

At 65nm, OPC may be necessary on several more metal layers. While vendors are hesitant to reveal exactly which layers require OPC, Intel's Bohr did say that in the company's 65nm process, Metal-1 through Metal-3 all had to be exposed on 193nm steppers. Presumably, they all require OPC as well.

"I can say that we have put considerable effort into OPC, making sure that the features we're creating are the geometries the designers intended," Martin said. "This is especially true in the 1x layers!those with the finest metal pitch."

Layers that require OPC also need very intimate interaction among process engineers, mask makers and the chip physical design team, to make sure that the designers' intent is being honored in the metal. When OPC use was limited to Metal-1, this only meant that cell designers had to work closely with the fab!which is nothing new. But as the requirement moves up the interconnect stack, that fellowship may have to be extended even to designers who are simply placing and routing standard-cell designs. It is easy for existing place-and-route tools to create patterns incompatible with OPC.

"Right now, we are on the threshold of the point where layers created by the design team will require inspection for OPC compatibility," Martin said. "At some point soon, we'll have to work together closely with design teams on the ability to create mask patterns that can render their intent."

That close relationship already has to exist for another area of checks!dimensional control!and it will only become more intimate at 65nm.

Even if the right patterns are created in the photoresist, there are several problems to be solved before the right shapes actually exist in the metal and dielectric materials. Chemical-mechanical polishing is one of the hurdles. The interaction between the rotating polishing disk, the polishing material and the surface of the wafer is quite complex and!unfortunately for designers!highly pattern-dependent. The orientation and shape of lines and especially their spatial distribution will determine how much metal is removed during polishing.

Other variations arise from the lithography process, where variations in focus can cause width variations; in deposition, where the thickness of films can vary; and in etching, which can introduce further variations while translating an opening in a resist layer into a trench in the underlying material. All of these accumulate and translate into variations in the resistance and capacitance of interconnect segments.

"Modeling interconnect delay is a serious issue," Bohr said. "Now we are at the point where we simply need more complex models to reflect the expected shape of the interconnect as you go through various sizes of segments and different vias. Simple lumped models aren't going to cut it."

But starting perhaps just beyond 65nm, the problem will get worse. Bohr warned that the variations in interconnect geometry were approaching the importance of those widely discussed variations in transistor parameters. "Already, it's not feasible to do worst-case design. You have to account for transistor variations with some sort of statistical design technique, or you leave too much on the table and produce an uncompetitive design," Bohr said. "That's gradually becoming true for interconnect as well. But we aren't there yet at 65nm."

One reason we aren't there yet is the heroic effort on the part of process integration engineers. Intel, for example, has attacked problems in via formation so successfully that its design rules do not require redundant vias in signal paths. "There are things you can do, such as filling the vias with copper and doing barriers correctly, that help with via formation," Bohr said.

Chartered, with its process development partners IBM, Infineon and Samsung, is fighting a similar battle on dimensional variations. "A big factor is the automated precision manufacturing (APM) process control system Chartered has licensed from Analog Micro Devices," Martin said. "One of the focuses of APM is the polishing process and controlling the variability it can create. Our data so far indicates that it will be effective in our foundry environment and in AMD's mass-production environment."

"But another important component," Martin added, "will be working with design teams to control the pattern density across the die so that the polisher is working on a relatively uniform surface."

Looking beyond 65nm, the path is less clear. As metal geometries shrink, it is critical to reduce the dielectric constant of the insulating material. But Bohr said so far, there have been only minor improvements in k. "We changed to a lower-k etch-stop layer, which helped the k-effective of the whole stack," he said. "But the best way we have of reducing capacitance between lines right now is to add metal layers to reduce congestion. We can't keep doing that forever."

"I expect that, by 45nm, we will have selected a suitable new dielectric material," Martin said. "There simply wasn't one available in time for 65nm that had appropriate mechanical and process-integration characteristics."

The candidates today remain problematic. "Copper in thin films!such as in lower metal layers!is very weak," observed David Wang, president and CEO of non-contact polishing vendor ACM Research Inc. "We can use mechanical polishing today because the thin metal ribbons get mechanical support from the dielectric material in which they are lying. But copper has a Young's modulus of about 40. The new low-k materials are around 3. They aren't going to support the copper, and it is going to be deformed beyond its elastic limit if you try to mechanically polish it and you aren't very careful."

The picture at 65nm remains guardedly optimistic, with almost no materials changes!none at all in Chartered's case!from 90nm. But 65nm designs will still require more effective process controls and closer work with design teams. At 45nm, there are still many answers missing. But no one will be able to take interconnect for granted.

- Ron Wilson

EE Times

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