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Implement component partitioning for system-in-package apps

Posted: 18 Jul 2005 ?? ?Print Version ?Bookmark and Share

Keywords:sip? system partitioning? time-to-market? soc? bom?

Timely and effective development of system-in-package (SiP) alternatives has driven the need for broader supplier collaboration on system-partitioning decisions within the electronics food chain. Unlike earlier generations of electronics that had individually packaged components, packaging subcontractors and semiconductor device manufacturers today must work together to define the most effective partition options available. A disciplined engineering methodology is required to ensure that these upstream engagements are facilitated in the early stages of the design cycle, with particular emphasis on optimizing SiP design up front.

The decision to design and implement an SiP solution is motivated by several factors. The most obvious is to reduce the complexity of an RF design, thus making implementation much easier for system designers who lack RF board-level design experience. Another reason would be to take advantage of using separate, fully optimized devices rather than a fully integrated design. In many cases, the SoC solution will not be as efficient as the SiP in terms of power consumption.

Embedded memory was once the holy grail for chip designers. But as competition rose and prices slipped, SoC integration of memory was deemed too expensive to compete with stacked-dice packaging alternatives. Thus, a vast array of memory and logic stacked-dice packages is available in wlan and other cost-sensitive consumer applications.

Another factor influencing the implementation of SiP is time-to-market. Often, an SoC can involve longer development cycles of as much as 18 months, with larger, more complex devices and higher risk. Failure to stay on schedule can put a company out of business. Therefore, many companies view SiP as a hedge against missed or delayed development cycles in standard SoC implementations.

An SiP's design can be influenced by constraints of the package such as overall size and height, with the latter being a common limiting factor for passive-component inclusion. The preferred way to begin partitioning a design is to start with a schematic, bill-of-materials, package type and required physical package size including height. Passive components can have tall profiles and the first order of partitioning is to sort out which components will fall under the height restriction dictated by the package size parameters.

Once this initial partitioning is complete, a second schematic that reflects the package-to-system boundaries is created. It is important for the system designer to be involved early on in the partitioning, since choices made here can affect the overall performance and functionality of the resultant SiP assembly.

Once the system designer approves the basic partition, the mechanical and thermal limits for the SiP are evaluated by simulation. Any potential solution may have hidden issues, so these simulations are designed to ensure that the package can dissipate enough heat to keep the dice under the maximum junction temperature and ensure mechanical stability when thermal cycles are encountered. Once verified as the proper platform to satisfy all thermal and mechanical requirements, the next step is to refine the layout of the SiP.

Filters realized in SiP will need to have the capacitor values changed once the package parasitics are known. This phase of design consists of generation and layout of the critical nets first, followed by simulation of the nets for electrical-performance considerations, including impedance control, timing, crosstalk and insertion loss.

When these critical nets are taken care of, the remaining nets are routed. Once completely routed, the critical nets are once again simulated; this time, the electrical performance is examined with emphasis on coupling between adjacent nets. Mutual inductance and capacitance need to be accounted for, as well as shunt capacitance in filters. Not accounting for all of the potential sources of capacitance in a filter or balun generally results in operation off center frequency and poor performance in return loss.

Monte Carlo simulations are effective in looking at how wide a component's tolerance can be in a passive network such as in image rejection filters. Certainly, passives with 1 percent tolerance will have better overall response than those with 5 percent. However, in some cases, the 5 percent components do not produce enough skew to pull the passive network off specification. To avoid unnecessary additional cost, it is imperative to match passives' tolerance to the application limits.

Once the simulations and data analysis are finalized, a clear picture will emerge for the passive values that can be tolerated and the BoM will be completed with components that deliver performance with the lowest cost. From this point onward, the program runs in the same manner as any other package program with qualification and manufacturing ramp-up.

Finding the right solution for SiP involves partitioning the bill-of-materials based on derived package constraints. Mechanical and thermal simulations are then used to ensure that the package constraints do not render the device too hot or mechanically unstable. Layout and electrical simulation are the cornerstones of first-pass success, which can only be realized by using a well-correlated simulation tool. Such tools require countless hours of measurement and prediction analysis. Without this correlated tool, many designs will be respun a number of times before the SiP is market-ready.

There are many other decisions that need to be made along the way, such as the choice of laminate substrate material (green, or lead-free) and solder alloy composition. All of these will affect cost and reliability. Each SiP solution will be somewhat unique, requiring new process techniques or materials development.

Without early engagement with SiP system designers, many of the issues and trade-offs that need to be solved before ramping products go unanswered. Hence, debug time may become lengthy as a more traditional plug-and-chug approach ensues. This traditional approach involves changing passive values to pull the filter on center frequency. Careful planning, upstream engagement and well-correlated simulation tools are necessary for first-pass success and quick time-to-market.

Dean Kossives

Ted Tessier

Technical Staff, Advanced Packaging Technology Group

ST Assembly Test Services Ltd

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