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SiP modules call for right blend of tech

Posted: 18 Jul 2005 ?? ?Print Version ?Bookmark and Share

Keywords:Agere Systems Inc.?

System-in-package (SIP) solutions offer a seemingly limitless combination of silicon, package and component technologies. They can provide enough integration to complement SoC applications by using existing silicon or components that can be combined to perform in the same manner as sophisticated SoC dice, without new silicon design costs or risks. Reusing existing technology reduces time-to-market while potentially offering higher overall package yields. Additionally, SiP modules can integrate complex design, tuning and testing while offering drop-in solutions that simplify overall system design.

One example of a recent SiP solution is a lead-frame-based SiP design aimed at high-volume consumer storage markets. By combining an SoC with previously external buffer memory in a low-cost, exposed-pad thin QFP, designers achieved a 50 percent form-factor reduction, simplified board routings and improved electrical performance over the individually packaged devices. The challenges of this approach were maintaining a tightly coupled co-design process on the SoC and memory interconnect pad layout, thermal modeling of the die pad design and, finally, ensuring adequate fault coverage on two different test platforms to guarantee outgoing defects-per-million levels.

Another example is a highly integrated 802.11b RF Wi-Fi SiP with five dice and more than 120 surface-mounted active and passive components in a shielded package. Despite the design's complexity, average final test yields exceeded targets while achieving footprint and cost goals. The SiP integrates all of the complex RF design and arrives as a fully tuned plug-and-play unit for wireless gaming and VoIP markets.

Finally, a 45mm body-size SiP design for data-mapping applications demonstrates the use of advanced packaging techniques for fast integration of current silicon solutions to provide customers with new, more powerful capabilities. The resulting SiP combined four data-mapper chips in a cost-effective, fast time-to-market alternative that delivers performance equivalent to a more expensive SoC solution that has lower yields and a longer time-to-market.

Tools, methodologies

Depending on the complexity of the SiP design, standard tools from Mentor Graphics, Cadence, Synopsys or AutoCAD can route layouts. Since SiP designs can vary, however, design rules for some applications may be pushed to the limit or simply not exist at all. SiP designers must therefore develop and then prove the robustness of ever-expanding SiP design rules for new applications.

Typically, critical routing is given priority. In the case of the Wi-Fi SiP, critical paths included the RF functional areas; in the lead-frame SiP, the die-to-die wire-bonding array routing was critical. But the developer must also remain aware of areas such as the assembly process, reliability and mechanical constraints as the design is being completed.

SiP signal routing can challenge designers because of the increased I/O counts and layer-to-layer interconnects required. For example, completion of the four-dice, 45mm SiP required advanced substrate design rules and high trace and plane-to-plane via densities.

Many standard, single-die packaging technologies can be used for SiPs, from small, low-I/O lead frames to large BGA packages exceeding 1,000 I/Os. Die arrangements can be stacked, arranged side by side or a combination of the two. Passive components can be surface-mounted or embedded in the substrate. For optimum SiP performance, die-to-die interconnectivity must be determined early in the design process to ensure proper signal integrity and manufacturability.

The Wi-Fi SiP used a multilayer BT laminate PBGA substrate that met RF performance criteria without having to use more costly substrate material. A metal shield was attached that provided RF shielding from the outside environment and shielded specific areas within the module itself.

The four-dice, 45mm, 1,152-I/O SiP used standard BT PBGA substrate technology. Symmetrically positioning four 14-by-14mm, 700-I/O (in packaged form) wire-bonded dice on the substrate allowed for an I/O reduction (due to some commonality of power, ground and signals) of 59 percent over the four individually packaged dice.

Test implications

SiP test yield is influenced by the yield of the individual components. As component count increases, so does the need for known-good-dice or high wafer-level test coverage to achieve an SiP with acceptable final yields. Design-for-test is highly effective in increasing SiP yields and should be integral to silicon and package design.

Today, SiPs provide compact, high-performance alternatives to discrete multichip implementations in cases where full SoC integration may be too costly or too complex. SiP implementations are also proving nearly as diverse as their markets. Just as design, test and packaging are important in SoC, SiP requires careful balancing of those key processespossibly to an even greater degree than for SoCsto achieve functional, cost-efficient products.

Lawrence Golick, Jason Goodelle and Thomas Shilling

Technical Staff

Agere Systems Inc.




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