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HHNEC develops three series PLL IPs

Posted: 20 Jul 2005 ?? ?Print Version ?Bookmark and Share

Keywords:frequency synthesizers? soc? on-chip clock generation? ip? 0.25µm cl250g?

Shanghai Hua Hong NEC Electronics Co. Ltd (HHNEC) has developed a series of high performance frequency synthesizers for SOC clock generation IPs used in 0.25?m CL250G process.

The IP series HQCOMPLDLR00V1, HQCOMPLDMR00V1 and HQCOMPLDHR00V1, is targeted for applications that are cost sensitive, with small area single ended PLL, high power supply noise rejection differential PLL and high frequency on-chip clock generation PLL. Meanwhile, 300?m-by-350?m die size is achieved for die size reduction SOC designs.

For differential series PLL, 250MHz clock frequency with 15ps RMS lower jitter specification can be readily achieved. For high frequency clock generation requirement designs, up to 572MHz can be provided with internal VCO oscillating frequency as high as 1.9GHz. With these PLL IP, HHNEC is confident that SOC designers can focus on their key technology and reduce their product development and time-to-market.

HHNEC claims to be the first 8-inch wafer foundry provider in China with CMOS process technology, manufacturing equipment and ISO certification (both ISO9001 and ISO14001), as well as BS7799 qualified service support system.

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