Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

New utility accelerates Virtex-4 FPGA speeds by 26 percent

Posted: 20 Jul 2005 ?? ?Print Version ?Bookmark and Share

Keywords:virtex-4? spartan-3? field-programmable gate array? fpga? xilinx?

To help designers benchmark and maximize the performance benefits of Virtex-4 and Spartan-3 FPGAs, Xilinx Inc. is offering the Xplorer utility that when used with rtl level retiming with the company's ISE software claims it can improve Virtex-4 device performance by 26 percent.

The Xplorer utility is said to save designers a full speed-grade compared with competing 90nm FPGAs. It employs smart constraining techniques and a variety of physical optimization strategies.

Xplorer works with the Xilinx ISE software suite to explore the right set of options to meet design constraints. Xilinx realized the 26 percent performance improvement results by conducting a benchmarking experiment on more than 50 customer designs.

The Xplorer utility was also used with a suite of synthesizable RTL designs from OpenCores. It can be downloaded free of charge at Xilinx's website.

eeProductCenter




Article Comments - New utility accelerates Virtex-4 FPG...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top