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Cadence Encounter RTL to perform Canon's future tapeouts

Posted: 22 Jul 2005 ?? ?Print Version ?Bookmark and Share

Keywords:canon? encounter rtl compiler? asic?

Cadence Design Systems Inc. announced that Japan-based Canon Inc. has adopted its Encounter RTL compiler for ASIC designs. Yasuhiro Tani, senior general manager, SOC design at Canon said that the evaluations of their previous ASIC designs using Encounter RTL compiler have shown consistent benefits.

"We have adopted Encounter RTL compiler for future tapeouts because of its ability to increase chip performance, reduce power, reduce turnaround time and increase productivity. We will now make support for Encounter RTL compiler a requirement for our ASIC vendors," Tani added.

According to Cadence, interconnect related parameters in nanometer designs require a new metric for synthesis results that includes performance, area, and power measured with wires. The company defines this as quality-of-silicon (QoS). The Encounter RTL compiler's global synthesis enables designers to achieve the highest QoS in less time and with less effort, Cadence stated.

Chi-Ping Hsu, corporate VP at Cadence, commented, "Encounter RTL Compiler is now being successfully used in production by companies throughout the world to achieve a competitive advantage via the fastest path to the highest QoS."

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