Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

SMIC and Synopsys announce reference design flow 2.0

Posted: 22 Jul 2005 ?? ?Print Version ?Bookmark and Share

Keywords:galaxy design platform? smic? rtl-to-gdsii?

Synopsys Inc. and Semiconductor Manufacturing International Corp. (SMIC) said Tuesday (July 19) that they have developed a new RTL-to-GDSII reference flow based on Synopsys' Galaxy design platform and SMIC's 130nm process.

New features in version 2.0 of the SMIC-Synopsys reference flow include advanced floor planning capabilities from Synopsys' JupiterXT design planning solution, the companies said - specifically power network synthesis and power network analysis capabilities used to design the power plan at the floor planning stage.

Reference flow version 2.0 features advanced signal integrity (SI) and IC reliability analysis capabilities using Synopsys PrimeTime SI, Astro-Xtalk and Astro- Rail tools, according to Synopsys and SMIC. These features target electro-migration challenges that commonly cause increased resistance in power grid paths and lead to increased IR drop or ground bounce, the companies said.

Version 2.0 also introduces voltage-drop analysis.

"Working closely with SMIC has enabled us to deliver reference flows that address the advanced deep sub micron process needs of the growing Chinese market," said Rich Goldman, vice president of strategic market development at Synopsys, in a statement.

The companies said reference design flow 2.0 is available now through SMIC.

- Dylan McGrath

EE Times





Article Comments - SMIC and Synopsys announce reference...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top